Hardware Functional Specification - SE Spezial-Electronic AG
Hardware Functional Specification - SE Spezial-Electronic AG
Hardware Functional Specification - SE Spezial-Electronic AG
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Page 36 Epson Research and Development<br />
Vancouver Design Center<br />
7.4 Power Save Mode/Display Enable Timing<br />
Symbol Parameter<br />
t1a<br />
t1b<br />
t1c<br />
WR#<br />
YDIS<br />
Table 7-7 Power Save Mode/Display Enable Timing<br />
YDIS falling edge delay for Power Save Mode<br />
Enable in Indirect Mode (see Note 2)<br />
YDIS falling edge delay for Display Off in Indirect<br />
Mode (58h)<br />
YDIS falling edge delay for Display Off in Direct<br />
Mode (see Note 3)<br />
t1 t2<br />
Display On Display Off or Power Save Mode Enabled<br />
Display On<br />
1. Ts = System Clock Period<br />
2. Power Save Mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0.<br />
3. Display On/Off is controlled by the Display Enable bit, REG[09h] bit 0.<br />
S1D13700F00 <strong>Hardware</strong> <strong>Functional</strong> <strong>Specification</strong><br />
X42A-A-001-04 Issue Date: 2004/10/18<br />
Revision 4.0<br />
3.0 Volt 5.0 Volt<br />
Min. Max. Min. Max.<br />
Units<br />
⎯ 2 ⎯ 2 Frames<br />
⎯ 1Ts + 10 ⎯ 1Ts + 10 ns<br />
⎯ 2Ts + 10 ⎯ 2Ts + 10 ns<br />
t2 YDIS rising edge delay for Display On (see Note 3) ⎯ 2Ts + 10 ⎯ 2Ts + 10 ns
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