Hardware Functional Specification - SE Spezial-Electronic AG

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Page 34 Epson Research and Development Vancouver Design Center 7.3.5 M6800 Family Bus Indirect Interface Timing CS# AB[15:0], WR# (RW#, MR#) AS# RD# (UDS#, LDS#) DB[7:0] (write) DB[7:0] (read) t1 t2 t13 Figure 7-7 M6800 Family Bus Indirect Interface Timing Note CLK input to the M6800 interface must be driven synchronous to the host microprocessor. S1D13700F00 Hardware Functional Specification X42A-A-001-04 Issue Date: 2004/10/18 t4 t9 Revision 4.0 t3 t5 t6 t14 t10 t11 t12 t8 t7
Epson Research and Development Page 35 Vancouver Design Center Table 7-6 M6800 Family Bus Indirect Interface Timing Symbol Parameter 3.3 Volt Min Max 5.0 Volt Min Max Units t1 CS# setup time 5 ⎯ 5 ⎯ ns t2 AB[15:0] setup time 5 ⎯ 5 ⎯ ns t3 DB[7:0] setup time to RD# falling edge (write cycle) Note 2 ⎯ Note 2 ⎯ ns t4 RD# rising edge to DB[7:0] driven (read cycle) 3 ⎯ 3 ⎯ ns t5 CS# hold time 7 ⎯ 7 ⎯ ns t6 AB[15:0] hold time 7 ⎯ 7 ⎯ ns t7 DB[7:0] hold time from RD# falling edge (write cycle) 5 ⎯ 5 ⎯ ns t8 DB[7:0] hold time from RD# falling edge (read cycle) 2 55 2 55 ns t9 RD# rising edge to valid Data ⎯ Note 3 ⎯ Note 3 ns t10 RD# cycle time Note 4 ⎯ Note 4 ⎯ ns t11 RD# pulse active time 5 ⎯ 5 ⎯ Ts t12 RD# pulse inactive time Note 5 ⎯ Note 5 ⎯ ns t13 AS# setup time 0 ⎯ 0 ⎯ ns t14 AS# hold time 0 ⎯ 0 ⎯ ns 1. Ts = System clock period 2. t3min = 2Ts + 5 3. t9max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 4. t13min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 6. t15min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) Hardware Functional Specification S1D13700F00 Issue Date: 2004/10/18 X42A-A-001-04 Revision 4.0
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Hardware Functional Specification - SE Spezial-Electronic AG

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