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Hardware Functional Specification - SE Spezial-Electronic AG

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Page 18 Epson Research and Development<br />

Vancouver Design Center<br />

5.2.2 LCD Interface<br />

In order to provide effective low-power drive for LCD matrixes, the S1D13700F00 can<br />

directly control both the X and Y-drivers using an enable chain.<br />

Pin Name Type Pin # Cell Power RE<strong>SE</strong>T#<br />

State<br />

FPDAT[3:0]<br />

(XD[3:0])<br />

FPSHIFT<br />

(XSCL)<br />

O 18-21 OB2T NIOVDD X<br />

O 23 OB2T NIOVDD X<br />

XECL O 24 OB2T NIOVDD X<br />

FPLINE<br />

(LP)<br />

MOD<br />

(WF)<br />

O 26 OB2T NIOVDD X<br />

O 27 OB2T NIOVDD X<br />

YSCL O 29 OB2T NIOVDD X<br />

FPFRAME<br />

(YD)<br />

O 30 OB2T NIOVDD X<br />

YDIS O 31 OB2T NIOVDD L<br />

Table 5-3 LCD Interface Pin Descriptions<br />

S1D13700F00 <strong>Hardware</strong> <strong>Functional</strong> <strong>Specification</strong><br />

X42A-A-001-04 Issue Date: 2004/10/18<br />

Revision 4.0<br />

Description<br />

These output pins are the 4-bit X-driver (column drive) data<br />

outputs and must be connected to the inputs of the X-driver chips.<br />

The falling edge of FPSHIFT latches the data on FPDAT[3:0] into<br />

the input shift registers of the X-drivers. To conserve power, this<br />

clock is stopped between FPLINE and the start of the following<br />

display line.<br />

The falling edge of XECL triggers the enable chain cascade for the<br />

X-drivers. Every 16th clock pulse is output to the next X-driver.<br />

FPLINE latches the signal in the X-driver shift registers into the<br />

output data latches. FPLINE is a falling edge triggered signal, and<br />

pulses once every display line. FPLINE must be connected to the<br />

Y-driver shift clock on LCD modules.<br />

This output pin is the LCD panel backplane bias signal. The MOD<br />

period is selected using the SYSTEM <strong>SE</strong>T command.<br />

The falling edge of YSCL latches the data on FPFRAME into the<br />

input shift registers of the Y-drivers. YSCL is not used with driver<br />

ICs which use FPLINE as the Y-driver shift clock.<br />

This output pin is the data pulse output for the Y drivers. It is active<br />

during the last line of each frame, and is shifted through the Y<br />

drivers one by one (by YSCL), to scan the display’s common<br />

connections.<br />

This output pin is the power-down output signal. YDIS is high while<br />

the display drive outputs are active. YDIS goes low one or two<br />

frames after the power save command is written to the<br />

S1D13700F00. All Y-driver outputs are forced to an intermediate<br />

level (de-selecting the display segments) to blank the display. In<br />

order to implement power-down operation in the LCD unit, the LCD<br />

power drive supplies must also be disabled when the display is<br />

disabled by YDIS.

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