Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
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<strong>8080</strong> N/B Maintenance<br />
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)<br />
AC’97 Link Signals<br />
Signal Name Type Description<br />
AC_RST# O AC ’97 Reset: This signal is a master hardware reset to external<br />
Codec(s).<br />
AC_SYNC O AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the<br />
Codec(s).<br />
AC_BIT_CLK I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock<br />
generated by the external Codec(s). This signal has an integrated<br />
pull-down resistor.<br />
AC_SDOUT O AC97 Serial Data Out: Serial TDM data output to the Codec(s).<br />
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a<br />
functional strap.<br />
AC_SDIN[1:0] I AC97 Serial Data In 2:0: These signals are Serial TDM data inputs<br />
from the three Codecs.<br />
NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK<br />
Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of<br />
Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled.<br />
General Purpose I/O Signals<br />
Signal Name Type Description<br />
GPIO[43:32] I/O Can be input or output. Main power well.<br />
GPIO[31:29] O Not implemented.<br />
GPIO[28:27] I/O Can be input or output. Resume power well. Unmuxed.<br />
GPIO[26] I/O Not implemented.<br />
GPIO[25] I/O Can be input or output. Resume power well. Unmuxed.<br />
GPIO[24:18] I/O Not Implemented in Mobile (Assign to native Functionality).<br />
GPIO[17:16] O Fixed as Output only. Main power well. Can be used instead as<br />
PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for<br />
PCI GNT[5]#. Integrated pull-up resistor.<br />
GPIO[15:14] I Not implemented.<br />
GPIO[13:12] I Fixed as Input only. Resume power well. Unmuxed.<br />
GPIO[11] I Fixed as Input only. Resume power well. Can be used instead as<br />
SMBALERT#.<br />
GPIO[10:9] I Not implemented.<br />
GPIO[8] I Fixed as Input only. Resume power well. Unmuxed.<br />
GPIO[7] I Fixed as Input only. Main power well. Unmuxed.<br />
GPIO[6] I Not Implemented in Mobile (Assign to Native Functionality)<br />
GPIO[5:2] I Fixed as Input only. Main power well. Can be used instead as<br />
PIRQ[E:H]#.<br />
GPIO[1:0] I Fixed as Input only. Main power well. Can be used instead as<br />
PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI<br />
REQ[5]#.<br />
NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO<br />
are not 5V tolerant.<br />
Power and Ground Signals<br />
Signal Name Description<br />
VCC3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5<br />
or G3 states.<br />
VCC1_5 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3<br />
states.<br />
VCCHI 1.5 V supply for Hub Interface 1.5 logic.<br />
1.8 V supply for Hub Interface 1.0 logic.<br />
This power may be shut off in S3, S4, S5 or G3 states.<br />
V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in<br />
S3, S4, S5 or G3 states.<br />
HIREF Analog Input. Expected voltages are:<br />
0.9 V for HI 1.0 (Normal Hub Interface) Series Termination<br />
350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination<br />
This power is shut off in S3, S4, S5, and G3 states.<br />
VCCSUS3_3 3.3 V supply for resume well I/O buffers. This power is not expected to be shut<br />
off unless the main battery is removed or completely drained and AC power is<br />
not available.<br />
VCCSUS1_5 1.5 V supply for resume well logic. This power is not expected to be shut off<br />
unless the main battery is removed or completely drained and AC power is not<br />
available.<br />
V5REF_SUS Reference for 5 V tolerance on resume well inputs. This power is not expected<br />
to be shut off unless the main battery is removed or completely drained and AC<br />
power is not available.<br />
VCCLAN3_3 3.3 V supply for LAN Connect interface buffers. This is a separate power plane<br />
that may or may not be powered in S3–S5 states depending upon the presence or<br />
absence of AC power and network connectivity. This plane must be on in S0 and<br />
S1-M.<br />
VCCLAN1_5 1.5 V supply for LAN Controller logic. This is a separate power plane that may<br />
or may not be powered in S3–S5 states depending upon the presence or absence<br />
of AC power and network connectivity. This plane must be on in S0 and S1-M.<br />
VCCRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power<br />
is not expected to be shut off unless the RTC battery is removed or completely<br />
drained.<br />
NOTE: Implementations should not attempt to clear CMOS by using a jumper<br />
to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done<br />
by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.<br />
VCCPLL 1.5 V supply for core well logic. This signal is used for the USB PLL. This<br />
power may be shut off in S3, S4, S5 or G3 states.<br />
VBIAS RTC well bias voltage. The DC reference voltage applied to this pin sets a<br />
current that is mirrored throughout the oscillator and buffer circuitry.<br />
V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to<br />
drive the processor interface outputs.<br />
VSS Grounds.<br />
97
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