Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
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<strong>8080</strong> N/B Maintenance<br />
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)<br />
Processor Interface Signals (Continued)<br />
Signal Name Type Description<br />
CPUPWRGD OD CPU Power Good: This signal should be connected to the<br />
processor’s PWRGOOD input. To allow for Intel ® SpeedStep<br />
technology support, this signal is kept high during an Intel<br />
SpeedStep technology state transition to prevent loss of processor<br />
context. This is an open-drain output signal (external pull-up<br />
resistor required) that represents a logical AND of the ICH4’s<br />
PWROK and VGATE / VRMPWRGD signals.<br />
DPSLP# O Deeper Sleep: This signal is asserted by the ICH4 to the processor.<br />
When the signal is low, the processor enters the Deeper Sleep state<br />
by gating off the processor Core clock inside the processor. When<br />
the signal is high (default), the processor is not in the Deeper Sleep<br />
state. This signal behaves identically to the STP_CPU# signal, but<br />
at the processor voltage level.<br />
SMBus Interface Signals<br />
Signal Name Type Description<br />
SMBDATA I/OD SMBus Data: External pull-up is required.<br />
SMBCLK I/OD SMBus Clock: External pull-up is required.<br />
SMBALERT#/<br />
GPIO[11]<br />
I SMBus Alert: This signal is used to wake the system or generate<br />
SMI#. If not used for SMBALERT#, it can be used as a GPI.<br />
System Management Interface Signals<br />
Signal Name Type Description<br />
INTRUDER# I Intruder Detect: Can be set to disable system if box detected open.<br />
This signal’s status is readable, so it can be used like a GPI if the<br />
Intruder Detection is not needed.<br />
SMLINK[1:0] I/OD System Management Link: SMBus link to optional external<br />
system management ASIC or LAN controller. External pull-ups are<br />
required.<br />
Note that SMLINK[0] corresponds to an SMBus Clock signal, and<br />
SMLINK[1] corresponds to an SMBus Data signal.<br />
Real Time Clock Interface Signals<br />
Signal Name Type Description<br />
RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.<br />
RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.<br />
Other Clock Signals<br />
Signal Name Type Description<br />
CLK14 I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz.<br />
This clock is permitted to stop during S1-M (or lower) states.<br />
CLK48 I 48 MHz Clock: This clock is used to run the USB controller. It runs<br />
at 48 MHz. This clock is permitted to stop during S1-M (or lower)<br />
states.<br />
CLK66 I 66 MHz Clock: This is used to run the hub interface. It runs at 66<br />
MHz. This clock is permitted to stop during S1-M (or lower) states.<br />
Miscellaneous Signals<br />
Signal Name Type Description<br />
SPKR O Speaker: The SPKR signal is the output of counter 2 and is<br />
internally “ANDed” with Port 61h bit 1 to provide Speaker Data<br />
Enable. This signal drives an external speaker driver device, which<br />
in turn drives the system speaker. Upon PCIRST#, its output state is<br />
0.<br />
NOTE: SPKR is sampled at the rising edge of PWROK as a<br />
functional strap.<br />
RTCRST# I RTC Reset: When asserted, this signal resets register bits in the<br />
RTC well and sets the RTC_PWR_STS bit (bit 2 in<br />
GEN_PMCON3 register).<br />
NOTES:<br />
1. Clearing CMOS in an ICH4-based platform can be done by using<br />
a jumper on RTCRST# or GPI, or using SAFEMODE strap.<br />
Implementations should not attempt to clear CMOS by using a<br />
jumper to pull VccRTC low.<br />
2. Unless entering the XOR Chain Test Mode, the RTCRST# input<br />
must always be high when all other RTC power planes are on.<br />
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