Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
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<strong>8080</strong> N/B Maintenance<br />
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)<br />
Hub Interface Signals<br />
Signal Name Type Description<br />
HI[11:0] I/O Hub Interface Signals<br />
HI_STB/HI_STBS I/O Hub Interface Strobe/ Hub Interface Strobe Second: One of two<br />
differential strobe signals used to transmit and receive data through<br />
the hub interface.<br />
Hub Interface 1.5 mode this signal is not differential and is the<br />
HI_STB#/<br />
HI_STBF<br />
second of the two strobe signals.<br />
I/O Hub Interface Strobe Complement / Hub Interface Strobe First:<br />
One of two differential strobe signals used to transmit and receive<br />
data through the hub interface.<br />
Hub Interface 1.5 mode this signal is not differential and is the first<br />
of the two strobe signals.<br />
HICOMP I/O Hub Interface Compensation: Used for hub interface buffer<br />
compensation.<br />
HI_VSWING I Hub Interface Voltage Swing: Analog input used to control the<br />
voltage swing and impedance strength of hub interface pins.<br />
LAN Connect Interface Signals<br />
Signal Name Type Description<br />
LAN_CLK I LAN I/F Clock: Driven by the LAN Connect component.<br />
Frequency range is 5 MHz to 50 MHz.<br />
LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to<br />
transfer data and control information to the integrated LAN<br />
Controller. These signals have integrated weak pull-up resistors.<br />
LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals<br />
to transfer data and control information to the LAN Connect<br />
component.<br />
LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync<br />
signals are multiplexed onto this pin.<br />
EEPROM Interface Signals<br />
Signal Name Type Description<br />
EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM.<br />
EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the ICH3.<br />
This signal has an integrated pull-up resistor.<br />
EE_DOUT O EEPROM Data Out: Transfers data from the ICH3 to the<br />
EEPROM.<br />
EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM.<br />
Firmware Hub Interface Signals<br />
Signal Name Type Description<br />
FWH[3:0]/<br />
LAD[3:0]<br />
FWH[4]/<br />
LFRAME#<br />
I/O Firmware Hub Signals. Muxed with LPC address signals.<br />
I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME#<br />
signal.<br />
PCI Interface Signals<br />
Signal Name Type Description<br />
AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data<br />
bus. During the first clock of a transaction, AD[31:0] contain a<br />
physical address (32 bits). During subsequent clocks, AD[31:0]<br />
contain data. The ICH4 drives all 0s on AD[31:0] during the address<br />
phase of all PCI Special Cycles.<br />
C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable<br />
signals are multiplexed on the same PCI pins. During the address<br />
phase of a transaction, C/BE[3:0]# define the bus command. During<br />
the data phase, C/BE[3:0]# define the Byte Enables.<br />
C/BE[3:0]# Command Type<br />
0 0 0 0 Interrupt Acknowledge<br />
0 0 0 1 Special Cycle<br />
0 0 1 0 I/O Read<br />
0 0 1 1 I/O Write<br />
0 1 1 0 Memory Read<br />
0 1 1 1 Memory Write<br />
1 0 1 0 Configuration Read<br />
1 0 1 1 Configuration Write<br />
1 1 0 0 Memory Read Multiple<br />
1 1 1 0 Memory Read Line<br />
1 1 1 1 Memory Write and Invalidate<br />
All command encodings not shown are reserved. The ICH4 does not<br />
decode reserved values, and therefore will not respond if a PCI<br />
master generates a cycle using one of the reserved values.<br />
DEVSEL# I/O Device Select: The ICH4 asserts DEVSEL# to claim a PCI<br />
transaction. As an output, the ICH4 asserts DEVSEL# when a PCI<br />
master peripheral attempts an access to an internal ICH4 address or<br />
an address destined for the hub interface (main memory or AGP).<br />
As an input, DEVSEL# indicates the response to an ICH4-initiated<br />
transaction on the PCI bus. DEVSEL# is tri-stated from the leading<br />
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until<br />
driven by a Target device.<br />
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