Mitac 8080 Service Manual - laptop schematics, notebook ...

8080 N/B Maintenance
5.2 Intel 82855GM Graphics and Memory Controller Hub (GMCH)
Host Interface Signals (Continued)
Signal Name Type Description
HREQ[4:0]# I/O
AGTL+
HTRDY# O
AGTL+
RS[2:0]# O
AGTL+
Host Request Command: Defines the attributes of the request.
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting
agent during both halves of the Request Phase. In the first half the
signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second half the signals
carry additional information to define the complete transaction type.
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Status: Indicates type of response according to the
following the table:
RS[2:0] Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH-M)
100 Hard Failure (not driven by MCH-M)
101 No data response
110 Implicit Write back
111 Normal data response
DDR SDRAM Interface Signals
Signal Name Type Description
SCS [3:0]# O
SSTL_2
SMA[12:0] O
SSTL_2
SBA[1:0] O
SSTL_2
SRAS# O
SSTL_2
SCAS# O
SSTL_2
Chip Select: These pins select the particular DDR SDRAM
components during the active state.
Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM
device row. These signals can be toggled on every rising System
Memory Clock edge.
Multiplexed Memory Address: These signals are used to provide
the multiplexed row and column address to DDR SDRAM.
Bank Select (Memory Bank Address): These signals define which
banks are selected within each DDR SDRAM row. The SMA and
SBA signals combine to address every possible location within a
DDR SDRAM device.
DDR Row Address Strobe: SRAS# may be heavily loaded and
requires tw0 DDR SDRAM clock cycles for setup time to the DDR
SDRAMs. Used with SCAS# and SWE# (along with SCS#) to
define the System Memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and
requires two clock cycles for setup time to the DDR SDRAMs.
Used with SRAS# and SWE# (along with SCS#) to define the
System Memory commands.
Signal Name Type Description
SWE# O
SSTL_2
SDQ[71:0] I/O
SSTL_2
SDQS[8:0] I/O
SSTL_2
SCKE[3:0] O
SSTL_2
SMAB[5,4,2,1] O
SSTL_2
SDM[8:0] O
SSTL_2
RCVENOUT# O
SSTL_2
RCVENIN# I
SSTL_2
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
define the DDR SDRAM commands. SWE# is asserted during
writes to DDR SDRAM. SWE# may be heavily loaded and requires
two clock cycles for setup time to the DDR SDRAMs.
Data Lines: These signals are used to interface to the DDR
SDRAM data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64]
signals.
Data Strobes: Data strobes are used for capturing data. During
writes, SDQS is centered on data. During reads, SDQS is edge
aligned with data. The following list matches the data strobe with
the data bytes.
There is an associated data strobe (DQS) for each data signal (DQ)
and check bit (CB) group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
NOTE: ECC error detection is supported by the SDQS[8] signal.
Clock Enable: These pins are used to signal a self-refresh or power
down command to the DDR SDRAM array when entering system
suspend. SCKE is also used to dynamically power down inactive
DDR SDRAM rows. There is one SCKE per DDR SDRAM row.
These signals can be toggled on every rising SCK edge.
Memory Address Copies: These signals are identical to
SMA[5,4,2,1] and are used to reduce loading for selective
CPC(clock-per-command). These copies are not inverted.
Data Mask: When activated during writes, the corresponding data
groups in the DDR SDRAM are masked. There is one SDM for
every eight data lines. SDM can be sampled on both edges of the
data strobes.
NOTE: ECC error detection is supported by the SDM[8] signal.
Clock Output: Reserved, NC.
Clock Input: Reserved, NC.
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