Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
Mitac 8080 Service Manual - laptop schematics, notebook ...
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<strong>8080</strong> N/B Maintenance<br />
5.2 Intel 82855GM Graphics and Memory Controller Hub (GMCH)<br />
Host Interface Signals<br />
Signal Name Type Description<br />
ADS# I/O<br />
AGTL+<br />
BNR# I/O<br />
AGTL+<br />
BPRI# O<br />
AGTL+<br />
BREQ0# I/O<br />
AGTL+<br />
CPURST# O<br />
AGTL+<br />
DBSY# I/O<br />
AGTL+<br />
DEFER# O<br />
AGTL+<br />
DPSLP# I<br />
CMOS<br />
HD[63:0]# I/O<br />
AGTL+<br />
Address Strobe: The system bus owner asserts ADS# to indicate<br />
the first of two cycles of a request phase. The GMCH can assert this<br />
signal for snoop cycles and interrupt messages.<br />
Block Next Request: Used to block the current request bus owner<br />
from issuing a new request. This signal is used to dynamically<br />
control the CPU bus pipeline depth.<br />
Bus Priority Request: The GMCH is the only Priority Agent on the<br />
system bus. It asserts this signal to obtain the ownership of the<br />
address bus. This signal has priority over symmetric bus requests<br />
and will cause the current symmetric owner to stop issuing new<br />
transactions unless the HLOCK# signal was asserted.<br />
Bus Request 0#: The GMCH pulls the processor bus BREQ0#<br />
signal low during<br />
CPURST#. The signal is sampled by the processor on the<br />
active-to-inactive transition of CPURST#. The minimum setup time<br />
for this signal is 4 BCLKs. The minimum hold time is 2 clocks and<br />
the maximum hold time is 20 BCLKs. BREQ0# should be tristated<br />
after the hold time requirement has been satisfied.<br />
During regular operation, the GMCH will use BREQ0# as an early<br />
indication for PSB Address and Ctl input buffer and sense amp<br />
activation.<br />
CPU Reset: The CPURST# pin is an output from the GMCH. The<br />
GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M)<br />
is asserted and for approximately 1 ms after RESET# is deasserted.<br />
The CPURST# allows the processor to begin execution in a known<br />
state.<br />
Note that the ICH4-M must provide CPU strap set-up and<br />
hold-times around CPURST#. This requires strict synchronization<br />
between GMCH, CPURST# deassertion and ICH4-M driving the<br />
straps.<br />
Data Bus Busy: Used by the data bus owner to hold the data bus for<br />
transfers requiring more than one cycle.<br />
Defer: GMCH will generate a deferred response as defined by the<br />
rules of the GMCH’s Dynamic Defer policy. The GMCH will also<br />
use the DEFER# signal to indicate a CPU retry response.<br />
Deep Sleep #: This signal comes from the ICH4-M device,<br />
providing an indication of C3 and C4 state control to the CPU.<br />
Deassertion of this signal is used as an early indication for C3 and<br />
C4 wake up (to active HPLL). Note that this is a low-voltage<br />
CMOS buffer operating on the PSB VTT power plane.<br />
Host Data: These signals are connected to the CPU data bus.<br />
HD[63:0]# are transferred at 4x rate. Note that the data signals are<br />
inverted on the CPU bus.<br />
Signal Name Type Description<br />
DINV[3:0]# I/O<br />
AGTL+<br />
HA[31:0]# I/O<br />
AGTL+<br />
HADSB[1:0]# I/O<br />
AGTL+<br />
DRDY# I/O<br />
AGTL+<br />
HDSTBP[3:0]# I/O<br />
HDSTBN[3:0]# AGTL+<br />
HIT# I/O<br />
AGTL+<br />
HITM# I/O<br />
AGTL+<br />
HLOCK# I/O<br />
AGTL+<br />
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.<br />
Indicates if the associated signals are inverted or not. DINV[3:0]#<br />
are asserted such that the number of data bits driven electrically low<br />
(low voltage) within the corresponding 16-bit group never exceeds<br />
8.<br />
DINV# Data Bits<br />
DNIV[3]# HD[63:48]#<br />
DNIV[2]# HD[47:32]#<br />
DINV[1]# HD[31:16]#<br />
DINV[0]# HD[15:0]#<br />
Host Address Bus: HA[31:3]# connects to the CPU address bus.<br />
During processor cycles the HA[31:3]# are inputs. The GMCH<br />
drives HA[31:3]# during snoop cycles on behalf of Hub Interface.<br />
HA[31:3]# are transferred at 2x rate. Note that the address is<br />
inverted on the CPU bus.<br />
Host Address Strobe: HA[31:3]# connects to the CPU address bus.<br />
During CPU cycles, the source synchronous strobes are used to<br />
transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.<br />
Strobe Address Bits<br />
HADSTB[0]# HA[16:3]#, HREQ[4:0]#<br />
HADSTB[1]# HA[31:17]#<br />
Data Ready: Asserted for each cycle that data is transferred.<br />
Differential Host Data Strobes: The differential source<br />
synchronous strobes are used to transfer HD[63:0]# and<br />
DINV[3:0]# at the 4x transfer rate.<br />
Strobe Data Bits<br />
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#<br />
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]#<br />
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]#<br />
HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]#<br />
Hit: Indicates that a caching agent holds an unmodified version of<br />
the requested line. Also, driven in conjunction with HITM# by the<br />
target to extend the snoop window.<br />
Hit Modified: Indicates that a caching agent holds a modified<br />
version of the requested line and that this agent assumes<br />
responsibility for providing the line.<br />
Also, driven in conjunction with HIT# to extend the snoop window.<br />
Host Lock: All CPU bus cycles sampled with the assertion of<br />
HLOCK# and ADS#, until the negation of HLOCK# must be<br />
atomic, i.e. no Hub Interface snoopable access to System Memory is<br />
allowed when HLOCK# is asserted by the CPU.<br />
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