Mitac 8080 Service Manual - laptop schematics, notebook ...

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<strong>8080</strong> N/B Maintenance 4. Definition & Location of Major Components 4.1 Main Board (Side B) PU2 U3 U9 U4 U7 PU22 U11 PU23 J509 U15 U17 U21 U19 U3 : Intel 82801DBM ICH4-M U4 : PLL207-151 Clock Generator U7 : CH7011A TV Encode U9 : VT6307 IEEE1394 Controller U11 : LF-H80P LAN Buffer U15 : VT6105-LOM LAN Controller U17 : CB710 CardBus & Card Reader Controller U19 : System Flash BIOS U21 : TPS2211A Power Switch PU2 : TL594C Battery Charging PU22 : +1.25V_DDR/+2.5V_DDR Voltage Converter PU23 : LTC3728L +3V/+5V Voltage Converter 79
<strong>8080</strong> N/B Maintenance 5. Pin Descriptions of Major Components 5.1 Intel Pentium M Processor Signal Name Type Description A[31:3]# I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M processor system bus. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. ADSTB[1:0]# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]# BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. During a bus stall, the BPM[2:0]# BPM[3] O I/O current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents. This includes debug or performance monitoring tools. Signal Name Type Description BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# I/O BR0# is used by the processor to request the bus. The arbitration is done between the Intel Pentium M processor (Symmetric Agent) and the MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM chipset. COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details. D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups Data Group DSTBN#/DSTBP# DINV# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 DBR# O Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal. 80
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SERVICE SERVICE MANUAL MANUAL FOR F
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Contents 8080 N/B Maintenance 5.3 I
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1.1 Introduction 8080 N/B Maintenan
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8080 N/B Maintenance The NS PC87393
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LAN single chip : VT6105LOM PCMCIA
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8080 N/B Maintenance A high bandwid
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8080 N/B Maintenance - Video Overla
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8080 N/B Maintenance - 8-bit, 16-bi
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HUB Interface for ICH4 8080 N/B Mai
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8080 N/B Maintenance The integrated
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Supports serial interrupt protocol
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Fully programmable through serial p
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32bit PCI Bus-Master Interface 8080
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8080 N/B Maintenance 1.1.2.10 PCMCI
Page 29 and 30: 1.1.2.11 AC”97 Codec _ STAC9750 8
Page 31 and 32: 1.1.2.13 System Flash Memory (BIOS)
Page 33 and 34: 1.2 Other Functions 1.2.1 Hot Key F
Page 35 and 36: 1.2.4 LED Indicators 8080 N/B Maint
Page 37 and 38: 1.2.6 Fan Power On/Off Management 8
Page 39 and 40: 1.3 Peripheral Components 1.3.1 LCD
Page 41 and 42: Software configurable Low weight Op
Page 43 and 44: 1.4.1.3 Standby Mode 8080 N/B Maint
Page 45 and 46: 8080 N/B Maintenance 1.5 Appendix 1
Page 47 and 48: Continued to the previous table Aud
Page 49 and 50: 2.1.3 Right-side View 1 2 3 4 2.1.4
Page 51 and 52: 2.2 System Disassembly 8080 N/B Mai
Page 53 and 54: 2.2.1 Battery Pack Disassembly 8080
Page 55 and 56: 2.2.3 CPU Disassembly Figure 2-4 Re
Page 57 and 58: 8080 N/B Maintenance 7. Loosen the
Page 59 and 60: 8080 N/B Maintenance 5. Unscrew fou
Page 61 and 62: 2.2.6 DDR SDRAM Disassembly 8080 N/
Page 63 and 64: 8080 N/B Maintenance 6. Carefully t
Page 65 and 66: Reassembly 8080 N/B Maintenance 1.
Page 69 and 70: 8080 N/B Maintenance 6. Carefully,
Page 73 and 74: 2.2.12 Touch Pad Disassembly 8080 N
Page 75 and 76: 3.1 Main Board (Side A) - 1 8080 N/
Page 77 and 78: 8080 N/B Maintenance 3. Definition
Page 79: 8080 N/B Maintenance 4. Definition
Page 83 and 84: 5.1 Intel Pentium M Processor Signa
Page 85 and 86: 8080 N/B Maintenance 5.2 Intel 8285
Page 99 and 100: 6. System Block Diagram U17 CardBus
Page 101 and 102: 7.2 Error Codes Code 10h 11h 12h 13
Page 103 and 104: 7.3 Debug Tool 8080 N/B Maintenance
Page 105 and 106: 8.1 No Power No Power Is the notebo
Page 107 and 108: POWER IN P20 U504 PJ501 Micro Contr
Page 109 and 110: 8.1 No Power P20 U504 Micro Control
Page 111 and 112: 8.2 No Display +3V L517 L513 L14 L9
Page 113 and 114: 8080 N/B Maintenance 8.3 VGA Contro
Page 115 and 116: 8.4 External Monitor No Display 808
Page 117 and 118: 8.5 Memory Test Error Extend DDRAM
Page 119 and 120: 8080 N/B Maintenance 8.6 Keyboard (
Page 121 and 122: 8.7 Hard Drive Test Error Hard Driv
Page 123 and 124: 8.8 CD-ROM Drive Test Error 8080 N/
Page 125 and 126: 8.9 USB Test Error 8080 N/B Mainten
Page 127 and 128: 8.10 Audio Failure Audio Failure 1.
Page 129 and 130: AOUT_R C326 4.7µ From previous pag
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P18 U17 PCMCIA Controller CB710 P9
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P9 U3 I/O Controller Hub 82801DBM I
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P9 8.13 IEEE 1394 Failure +3V L19 1
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9. Spare Parts List - 2 Part Number
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9. Spare Parts List - 10 Part Numbe
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9. Spare Parts List - 12 Part Numbe
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5 8080_R03 Project Code : G038 5 4
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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5 Maximum length less than 0.5" fro
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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GND 5 5 Dedicate for USB2.0 can't u
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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12 AOUT_R 5 5 C326 C327 R645 AOUT_R
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VT6307L IDSEL: AD21 PCI REQ0# PCI G
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5 5 4 4 3 10 USBP0- J510 B L39 +VCC
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5 5 4 4 3 U510 20,21 SA[0..17] SA0
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5 5 4 4 3 +5V D 1 3 SW8 2 4 KI6 KI6
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5 5 4 4 3 D D BAV70LT1 BAV70LT1 PJ5
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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5 5 4 4 3 D D 1 2 GND 1 2 PC86 1000
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5 5 4 4 3 D D VID[0..5] +5V_P VID0
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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5 5 4 4 3 3 2 2 1 1 D D C C B B A A
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SERVICE MANUAL FOR 8080 Sponsoring
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