Mitac 8060 Service Manual - laptop schematics, notebook ...

SERVICE SERVICE MANUAL MANUAL FOR 

FOR 

8060 



8060 8060 


BY: Sissel Diao 

TESTING TECHNOLOGY DEPARTMENT / TSSC 

Dec . 2002

Contents 

8060 N/B Maintenance 

1. Hardware Engineering Specification ………………………………………………………………… 

1.1 Introduction …………………………………………………………………………………………………………. 

1.2 System Architecture ………………………………………………………………………………………………… 

1.3 Electrical Characteristic …………………………………………………………………………………………… 

1.4 Appendix : Voltage Identification Definition ……………………………………………………………………… 

2. System View and Disassembly ………………………………………………………………………... 

2.1 System View ………………………………………………………………………………………………………… 

2.2 System Disassembly ………………………………………………………………………………………………… 

3. Definition & Location of Connectors / Switches …………………………………………………….. 

3.1 Mother Board ……………………………………………………………………………………………………….. 

3.2 Audio DJ Board …………………………………………………………………………………………….……… 

3.3 DC to DC Board ……………………………………………………………………………………………………. 

MiTac Secret 

Confidential Document 

4. Definition & Location of Major Components ……………………………………………………….. 

4.1 Mother Board ……………………………………………………………………………………………………….. 

5. Pin Description of Major Component …….…………………………………………………………. 

5.1 Intel Mobile Pentium 4 Processor – M ……………………………………………………………………………. 

5.2 Intel 82845 Memory Controller Hub Mobile (MCH-M) ………………………………………………………… 

4 

4 

6 

19 

29 

30 

30 

33 

58 

58 

61 

62 

63 

63 

65 

65 

70 

1

Contents 


5.3 Intel 82801CAM I/O Controller Hub 3 (ICH30M) ………………………………………………………………. 

5.4 RTL8139C(L) Ethernet Controller ………………………………………………………………………………. 

5.5 PCI4410 PCMCIA Controller …………………………………………………………………………………….. 

6. System Block Diagram ……………………………………………………………………………….. 

7. Maintenance Diagnostics ……………………………………………………………………………… 

7.1 Introduction ………………………………………………………………………………………………………… 

7.2 Error Codes …………………………………………………………………………………………………………. 

7.3 Maintenance Diagnostics …………………………………………………………………………………………… 

8. Trouble Shooting ……………………………………………………………………………………… 

8.1 No Power …………………………………………………………………………………………………………….. 

8.2 No Display …………………………………………………………………………………………………………… 

8.3 VGA Controller Failure LCD No Display ………………………………………………………………………… 

8.4 External Monitor No Display ……………………………………………………………………………………… 

8.5 Memory Test Error ………………………………………………………………………………………………… 

8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………. 

8.7 Hard Driver Test Error ……………………………………………………………………………………………. 

8.8 CD-ROM Driver Test Error ………………………………………………………………………………………. 

8.9 PIO Port Test Error ………………………………………………………………………………………………… 

8.10 USB Port Test Error ………………………………………………………………………………………………. 

MiTac Secret 


75 

83 

86 

92 

93 

93 

94 

97 

98 

99 

104 

107 

109 

111 

113 

115 

117 

119 

121 

2

Contents 


8.11 Audio Failure ……………………………………………………………………………………………………… 

8.12 LAN Test Error …………………………………………………………………………………………………… 

8.13 PC Card Socket and IEEE1394 Failure ………….……………………………………………………………… 

9. Spare Parts List ……………………………………………………………………………………….. 

10. System Exploded Views ……………………………………………………………………………… 

11. Circuit Diagram ……………………………………………………………………………………… 

12. Reference Material ………………………………………………………………………………….. 

MiTac Secret 


123 

126 

128 

130 

143 

144 

175 

3

1.1 Introduction 


1. Hardware Engineering Specification 

1.1.1 General Description 

This document describes the system hardware engineer specification for 8060 portable notebook computer system.The 

8060 notebook computer is a new mainstream high performance thin and light notebook in the MiTAC notebook 

family. 

1.1.2 System Overview 

CPU 

Core logic 

System BIOS 

Memory 

VGA Controller 

IDE 

LCD Display 

Keyboard 

Touch Pad 

- Mobile P4 (Northwood), 1.4-2.2GHz or above 

- Mobile Celeron (Northwood), 1.4-1.8GHz or above 

- Intel 845MP + ICH3M 

- Insyde 512KB Flash EPROM - Include System BIOS, VGA BIOS 

MiTac Secret 


- 0MB Memory onboard ; Expandable to 1.0GB 

- 200-pin DDR Memory Slot x2, DDR-200/266 specifications (USER Upgradeable) 

- nVidia MAP17-440, integrated 64MB DDR VRAM; Support AGP4X; 

- Support Multi Monitor; 

- Support 2 IDE channel,Up to Ultra DMA 100 

- 15.2” TFT display; 15:10 wide screen, Resolution 1280 x 854 WXGA+ 

- Internal Key Matrix Keyboard 

- Intelligence Glide pad with 2 buttons. 

4

Continued to previous page 

Audio 

Audio DJ 

PCMCIA 

I/O Ports 

MiniPCI 

LAN/MDC 

Suspend Mode 

LED Indicator 


- Built-in AC97 V2.2 Codec 

- Sound Blaster Pro compatible 

- 3D stereo enhancement 

- Built-in mono microphone 

- Built-in 2 1W / 8ohm stereo speakers 

- 4 player buttons: Play/Pause, Next Track, Previous Track, Stop/Eject (support System Power-off play) 

- 1 push button and 1 LED for Audio DJ function On/Off (Push 1 second for turn-on, toggle for turn-off) 

- Automatically turn-off for CD player idle more than 5 minutes 

- Digital volume Up/Down control 

- Type II x1 or Type I x1; CardBus support - Non support Zoom Video/Audio Function 

- Bi-directional Parallel port (EPP/ECP) x 1 

- USB (support USB 1.1 and USB 2.0) port x 2 

- RJ-11 port x 1 

- RJ-45 port x 1 

- DC input x 1 

- Battery Connector x1 

- VGA monitor port x 1 

- Line-out (SPDIF) x 1 

- Mic-in x 1 

- Line-in 

- IEEE1394 x 1 

-FIR x 1 

- TV-Out x 1 (7Pin S-Video connector NTSC/PAL) 

MiTac Secret 


- 802.11b wireless LAN (optional) with built-in Antenna 

- 10/100 Base-T LAN - MDC 56K, V.90 Modem 

- POS (S1), Suspend to RAM (S3), Suspend to Disk (S4), Non support Wake Up on time 

- HDD, CD-ROM, NUM, CAP, SCROLL, Wireless LAN, Audio DJ PWR 

5

1. .2 System Architecture 

1.2.2 Function Description 

1.2.2.1 CPU 


Mobile Intel Pentium 4 / Northwood / Celeron processors with 400MHz FSB 

Capable of mFC-PGA processor package 

Support 12KB L1 Cache and 256/512KB L2 Cache (Depends On CPU) 

1.2.2.2 Core Logic 

Intel 82845MP Memory Control Hub 

- Support AGP2.0 (4X AGP) 

- Support 200 and 266 MHz DDR compliant devices, largest memory support 1GB 

- Hub Interface to ICH3-M 

MiTac Secret 


Intel 82801CAM I/O Controller Hub 3 (ICH3M) 

- PCI Local Bus Specification , Revision 2.2-compliant with support for 33MHz PCI operations 

- Integrated IDE controller supports Ultra ATA 100/66/33 

- Enhanced DMA Controller, Interrupt Controller, and Timer Functions 

- Low Pin Count (LPC) interface 

6

1.2.2.3 Memory 


Support 200/266MHZ SO-DIMM DDR Memory expandable to 1024MB (2 SO-DIMM DDR slot). 

Slot1 

64MB 

64MB 

64MB 

64MB 

64MB 

128MB 

128MB 

128MB 

128MB 

256MB 

256MB 

256MB 

512MB 

512MB 

Slot2 

0 

64MB 

128MB 

256MB 

512MB 

0 

128MB 

256MB 

512MB 

0 

256MB 

512MB 

0 

512MB 

Total 

64MB 

128MB 

192MB 

320MB 

576MB 

128MB 

256MB 

384MB 

640MB 

256MB 

512MB 

768MB 

512MB 

1024MB 

MiTac Secret 


Table 1. Memory Expansion Capacity 

7

1.2.2.4 I/O Ports 

CRT Port 

- Standard VGA compatible port 

- DDC1 and DDC2B compliant 

Pin 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

Signal 

RED 

GREEN 

BLUE 

Monitor Sense 

GND 

GND 

GND 

GND 

VCC 

GND 

Monitor Sense 

CRT DATA 

HSYNC 

VSYNC 

CRT CLK 


Description 

Red analog video output 

Green analog video output 

Blue analog video output 

Monitor Sense 

Ground 

Ground 

Ground 

Ground 

+5VDC 

Ground 

Monitor Sense 

Data from DDC monitor 

Horizontal Sync control 

Vertical Sync control 

Clock to DDC monitor 

Table 2. CRT Connector 

Figure 1. CRT Connector 

MiTac Secret 


8

Pin 

1 

2 

3 

4 

5 

6 

7 

7 Pins S-Video port for TV-Out 

- Support up 1024*768 resolution 

- Support PAL and NTSC system 

- Support Composite Output by a transfer cable 

Signal Name 

GND 

NC 

COMP 

GND 

CRMA 

NC 

LUMA 

Table 3. S-Video Port 

Description 

- 

- 

O 

- 

O 

- 

O 


System 

NTSC 

NTSC 

NTSC 

NTSC 

NTSC 

NTSC 

System 

PAL 

PAL 

PAL 

PAL 

PAL 

PAL 

Input(Active) Resolution 

320 x 320 

640 x 480 

720 x 480 

720 x 400 

800 x 600 

1024 x 768 

Input(Active) Resolution 

320 x 320 

640 x 480 

720 x 480 

720 x 400 

800 x 600 

1024 x 768 

Active TV Lines 

480 ~ 400 

480 ~ 400 

480 ~ 400 

480 ~ 400 

480 ~ 420 

480 

Active TV Lines 

540 ~ 500 

540 ~ 500 

540 ~ 500 

576 ~ 510 

600 ~ 510 

520 

MiTac Secret 


Table 4. TV Out Support Modes 

Over/Under Scan 

+ 

+ 

+ 

+ 

+ 

Over 

Over/Under Scan 

+ 

+ 

+ 

+ 

+ 

Under 

9

IEEE 1394 Port 


- Supports serial bus data rates of 100, 200, and 400Mbits/second 

- The Asynchronous and Isochronous data transfers are supported 

- One IEEE1394 port supported 

Pin 

1 

2 

3 

4 

Audio Ports 

Signal Name 

TPB- 

TPB+ 

TPA- 

TPA+ 

Description 

I/O 

I/O 

I/O 

I/O 

Table 5. IEEE1394 Port Figure 2. 1394 Connector 

-SPDIF 

- Microphone In & Line IN 

- Built In 2 high quality internal speaker (1W / 4 ohm with Box) 

- Built in 1 mono microphone 

- AC97 V2.2 compliance. 

MiTac Secret 


Plug Ear-Phone In 

Plug SPDIF Device In 

Plug External Microphone 

Internal Speaker 

Mute 

Mute 

Mute 

Internal Microphone 

Active 

Active 

Mute 

LED of SPDIF 

Off 

On 

Off 

10

RJ-11 


- Connection to Modem Daughter Board Connector 

- Support 56Kbps/V.90 

Pin 

1 

2 

3 

4 

RJ-45 

Signal Name 

NC 

LINE + 

LINE – 

NC 

Direction 

- 

I/O 

I/O 

- 

Table 6. Modem Port 

Description 

No Connect 

Phone Line Positive 

Phone Line Negative 

No Connect 

- full duplex 10 Base-T,100 Base-T Ethernet 

Pin 

1 

2 

3 

4 

5 

6 

7 

8 

Signal Name 

TX + 

TX – 

RX + 

TERM 1 

TERM 2 

RX 

TERM 3 

TERM 4 

Direction 

OUT 

OUT 

IN 

- 

- 

IN 

- 

- 

Table 7. LAN Port 

Description 

Transmit Data Ring 

Transmit Data Tip 

Receive Data Ring 

Internal termination resistor 


Receive Data Tip 



Figure 3. Modem Connector 

MiTac Secret 


Figure 4. LAN Connector 

11

Infrared interface supporting IRDA format 

- FIR IrDA 1.1 compliant. 

- HP-SIR supported. 

USB Ports 

- Two industry standard USB 2.0 ports 

- Support MAX. Power Current 500mA each port 

Pin 

1 

2 

3 

4 

Signal Name 

VCC 

DATA- 

DATA+ 

GND 

Parallel Port 

Direction 

- 

I/O 

I/O 

- 


Description 

USB Device Power (+5VDC) 

Balanced Data Negative 

Balanced Data Positive 

Ground 

Table 8. USB Port Figure 5. USB Connector 

MiTac Secret 


- Configurable as logical ports LPT1 , LPT2 or LPT3 

- EPP rev 1.7 & 1.9 compatible 

- ECP (IEEE 1284) compatible 

- Industry standard 25 Pins connector 

12

Pin 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

Case 

Signal Name 

STROBE# 

PD0 

PD1 

PD2 

PD3 

PD4 

PD5 

PD6 

PD7 

-ACK 

BUSY 

PE 

SLCT 

-AUTOFDXT 

-ERROR 

-INIT 

SLCTIN# 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

Direction 

O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I 

I 

I 

I 

O 

I 

O 

I 

- 

- 

- 

- 

- 

- 

- 

- 

- 

Table 9. Parallel Port 


Description 

Data Strobe 

PP Data bit 0 

PP Data bit 1 

PP Data bit 2 

PP Data bit 3 

PP Data bit 4 

PP Data bit 5 

PP Data bit 6 

PP Data bit 7 

Printer Acknowledge 

Printer Busy 

Paper Out 

Print Select Acknowledge 

Auto Line Feed 

Printer Error 

Reset Printer 

Ground 

Ground 

Ground 

Ground 

Ground 

Ground 

Ground 

Ground 

Ground 

Ground 

MiTac Secret 


Figure 6. Parallel Port Connector 

13

1.2.2.5 PC Card Slot 


One Type II/I slot supporting the 1997 PC Card standard,and including full R2 (16-bit) and 32-bit Cardbus data 

transfer 

TI PCI4410 (PCMCIA Controller) & TI TPS2211 (Power Switch) 

1.2.2.6 Graphical Subsystem 

nVidia NV17-MAP graphical controller embedded 64M DDR SDRAM 

AGP4X including power management pins 

Two channel LVDS interface 

TV-out support for NTSC and PAL 

692 PBGA Package 

1.2.2.7 Display 

MiTac Secret 


15.2” TFT display; 15:10 wide screen, Resolution 1280x854 WXGA+ 

External Video refresh rate of up to 100Hz supported 

- Vertical refresh frequencies to meet VESA requirements 

- Simultaneous video in specified video modes – switchable with hot key 

14

1.2.2.8 IDE Interface 


Support Dual Independent IDE Channels, One is Hard Disk. The other one is Optical Device 

Supports PIO mode 0,1,2,3,4 and Ultra DMA 33/66/100 

1.2.2.9 Read Only Memory (BIOS Flash) 

Fully compatible with industry standard software including Windows 2000 & Windows XP 

Fully supports APM V1.2 and latest ACPI specification 

4Mb Flash BIOS 

Insyde BIOS core 

1.2.2.10 Power Management Features 

Local standby mode (Individual devices such as HDD, graphics controller, LCD etc..) 

CPU Idle mode (Including ACPI modes C1 and C2) 

Suspend mode (Including S1 and S3 ACPI modes) 

Fully APM V1.2 compliant 

Fully ACPI V1.1 compliant 

MiTac Secret 


Hibernate for Windows 2000 and Windows XP 

15

Thermal management 

Fully US EPA Energy Start compliant 

1.2.2.11 Keyboard Controller 

Hitachi H8-3437S 

1.2.2.12 Super I/O 

NS PC87393F LPC interface Ultra I/O 

1.2.2.13 LEDs Indicator 


HDD & CDROM & NUM & CAP & SCROLL & Wireless LAN & Audio DJ POWER 

1.2.2.14 Buttons 

One Power Button 

7 Audio Control Buttons 

MiTac Secret 


16

1.2.2.15 Touch Pad Module 

Synaptics TM41P-350 with two Buttons 

1.2.2.16 Audio DJ 

Seven Audio Control Buttons 

- PLAY_PAUSE 

- NEXT_TRK/SCAN_FW 

- PREV_TRK/SCAN_RW 

- STOP_EJECT 

- Volume up (Digital Volume Control) 

- Volume Down (Digital Volume Control) 

- Power on / off Audio DJ 

Allowing CD play while the notebook is OFF 

Low power consumption 


MiTac Secret 


Automatically turn-off for CD player idle more than 5 minutes 

17

1.2.2.17 MODEM (MDC) - Option 

1.2.2.18 Mini PCI 

MiniPCI Specification V1.0 


Pin 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

Signal Name 

MONO_OUT 

NC 

NC 

NC 

NC 

NC 

NC 

GND 

+3V 

GND 

+3V 

ACSDOUT 

-ACRST 

GND 

GND 

Pin 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

Signal Name 

NC 

MODEM_SPK 

NC 

GND 

+5V 

NC 

NC 

Pull Up to +3V 

+5V 

GND 

ACSYNC 

MSDIN 

MSDIN 

GND 

ACBITCLK 

Table 10. Modem Daughter Board Connector 

MiTac Secret 


802.11b wireless LAN (optional) with built-in Antenna 

18

1.3 Electrical Characteristic 

1.3.1 Power On Sequence 

-PCIRST 

(9) -PCIRST 

VRMPWRGD 

-PCIRST 

CPU 

(Mobile Northwood) 

MCH-M 

(82845MP) 

ICH3M 

(10) -CPURST 

(82801CAM) 

PCI/AGP…Device 

(8) H_PWRGD 

(4) -RSMRST 

(5) +1.8V_ICH 

(7) VRMPWRGD 


DDR 

(7) PWROK 

(5) -PWRBTN 

(6) -SUSC 

(6) -SUSB 

(3) +3V_ICH 

R,C 

Regulator 

(AME8801) 

DDR_2.5V 

+3V_ICH 

DC/DC PWM 

Controller 

(LTC3707) 

+1.35VS +1.5VS +1.8VS +1.8VS 

MOSFET 

Regulator 

(TC55) 

+5V 

VMAIN Enable 

DC/DC PWM 

Controller 

(LTC3716) 

CPU_CORE 

Press Power Button 

Embeded Controller 

(H8-3437S) 

(2) PWR_ON 

DC/DC PWM 

Controller 

(MAX1632) 

+5V +12V +3V 

MOSFET 

+5VS +12VS +3VS 

Provide to 

system 

(CPU, NB..) 

(1) -POWERBTN 

MiTac Secret 


+12VS 

+5VA 

VMAIN 

-H8_RESET 

ADJ_ON 

Plug in AC Adapter 

or Main Battery 

VMAIN 

Regulator 

(LP2951) 

Reset Generator 

Circuitry 

(ADM809) 

Threshold : 4.38V 

DC/DC PWM 

Controller 

(LTC1735) 

+5V_CD 

Audio Device 

19

1.3.2 Power On Suspend Sequence 

1. Press LID 

2. Select Windows Standby 

3. Time Out 


1.3.3 Resume from Power On Suspend Sequence 

1. Ring In 

2. Press Keyboard/Mouse 

ICH3M 

(82801CAM) 

1. –STPCLK (High -> Low) 

2. After CPU Stop Grant Cycle, the 

ICH3M will output –CPUSLP (High -> Low) 

60~63 PCICLK 

ICH3M 

(82801CAM) 

1. –STPCLK (Low -> High) 

2. –SUS_STAT (Low -> High) ~10mS 

3. –CPUSLP (Low -> High) 2~4 PCICLK 

4. –STPCLK (Low -> High) 204~237uS 

(1) -STPCLK 

(3) -CPUSLP 

(2) PCI Stop Grant 

MiTac Secret 


(1) WAKE_UP 

(3) -STPCLK 

(2) -CPUSLP 

CPU 


Process Stop Grant Cycle 

PCI/AGP Device 

CPU 



20

1.3.4 Suspend To RAM Sequence 


EIDE Device .. 

MCH-M 

(82845MP) 


1. Press LID Button 

2. Select Windows Standby Function 

3. Press Internal Keyboard Fn+F12 

ICH3M 

(82801CAM) 

1. –STPCLK (High -> Low) 

2. After CPU Stop Grant, the ICH3M Output 

–CPUSLP 

3. –SUS_STAT (2~4 RTCCLK) High -> Low 

4. –PCIRST (9~15 RTCCLK) High -> Low 

5. –SUSB (1~2 RTCCLK) High -> Low 

(4) -PCIRSTMiTac Secret 

(1) -STPCLK 

(2) -CPUSLP 

(3) SUS_STAT 


(5) -SUSB 

CPU 



Graphics 

(NVIDIA NC17-MAP) 

Turn Off 

DC/DC 

Turn Off +1.5VS/+1.8VS/ 

+VDDR_MEM2.5V/+3VS 

+5VS/CPU_CORE 


(H8-3437S) 

Detect –SUSB Status 

21


1.3.5 Resume from Suspend To RAM Sequence 

1. Press LID Button 

2. Select Windows Standby Function 

3. Press Internal Keyboard Fn+F12 


EIDE Device .. 

MCH-M 

(82845MP) 

DC/DC PWM Controller 

(LTC3716 Power On 

Suspend Sequence) 

(1) -PCIRST 

ICH3M 

(82801CAM) 

1. –STPCLK (Low -> High) 

2. After CPU Stop Grant, the ICH3M Output 

–CPUSLP 

3. –SUS_STAT (2~4 RTCCLK) Low -> High 

4. –PCIRST (9~15 RTCCLK) Low -> High 

5. –SUSB (1~2 RTCCLK) Low -> High 

(4) -STPCLK 

(4) -CPUSLP 

(2) -SUSB 

(2) -SUSB 

(1) WAKE 

(5) PWROK 

MiTac Secret 


Press Power Button 

(4) VRMPWRGD DC/DC Circuitry 

(Turn On +1.5VS/+1.8VS/ 


+5VS/CPU_CORE) 

CPU 



Graphics 


Turn On 

DC/DC Circuitry 

(Turn On +1.5VS/+1.8VS/ 


+5VS/CPU_CORE) 

WAKE 

(3) -SUSB 


(H8-3437S) 

Detect –SUSB Status 

22

1.3.6 Suspend to Disk Sequence 

PCI Device 

(PCI4410, TRL8139CL, 

PC87393F) 

MCH-M 

(82845MP) 


ICH3M 

(82801CAM) 

1. STPCLK (High -> Low) 

2. Produce –CPUSLP 

3. –SUS_STAT (2~4 RTCCLK) High -> Low 

4. –PCIRST (9~15 RTCCLK) High -> Low 

5. –SUSB (1~2 RTCCLK) High -> Low 

6. –SUSC (1~2 RTCCLK) High -> Low 

7. VRMPWRGD and PWRGD High -> Low 

(4) -PCIRST (3) SUS_STAT 

D/D Board 

1. Received –SUSB, turn off +5VS, 

+3VS, +1.5VS, CPU_Core 

2. Received PWR_ON High -> Low, turn off 

1.8V, VDD_MEM2.5V, +3V, +5V, +12V 

CPU 


Produce Stop Grant Cycle 

(2) -CPUSLP (1) -STPCLK 

(5) -SUSB (8) -SUSC (6) PWROK 


(Hitachi H8-3437S) 

1. H8 Received -SUSC 

2. Send PWR_ON High -> Low 

VRMPWRGD 

MiTac Secret 


(7) PWR_ON 

+5V 

Graphics 


Turn Off 

PWM 

(LTC3716) 

1. Received +5V 

2. Send VRMPWRGD 

23


1.3.7 ICH3-M (82801CAM) GPI/O Pin Define 

GPIO6 

GPIO7 

GPIO8 

GPIO9 

GPIO10 

GPIO11/SMBALERT# 

GPIO12 

GPIO13 

GPIO14 

GPIO15 

GPIO18 

GPIO19 

GPIO20 

GPIO22 

Pin Name 

GPIO0/REQA# 

GPIO1/REQB#/REQ5# 

GPIO2/PIRQE# 

GPIO3/PIRQF# 

GPIO4/PIRQG# 

GPIO5/PIRQH# 

GPIO16/GNTA# 

GPIO17/GNTB#/GNT5# 

GPIO21/C3_STAT# 

TP 

-SCI 

-SMB_ALERT 

-EXTSMI 

TP 

Signal Name 

-PCI-REQA 

-PCI_REQB 

-PCI-INTE 

-PCI_INTF 

-PCI_INTG 

-PCI_INTH 

-AGP_BUSY 

-PCI_GNTA/TP 

-PCI_GNTB/TP 

-SUSA 

C3_STAT/TP 

-CPUPERF 

Power Plane 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3V_ICH 

+3.3V_ICH 

+3.3V_ICH 

+3.3V_ICH 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

Type 

Plane 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

O 

O 

O 

O 

O 

Original 

Type 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

O 

O 

O 

O 

O 

O 

OD 

During 

PCIRST# 

High - 2 

High - 2 

High - 2 

High - 2 

High 

High 

High - 2 

High - 2 

High 

High 

High - 2 

Immediately 

after PCIRST# 

High - 2 

High - 2 

High - 2 

High - 2 

High 

High 

High 

High 

High 

High 

High - 2 

Driven 

Driven 

High - 2 

High - 2 

High - 2 

High - 2 

High 

High 

Driven 

MiTac Secret 


S1 

High 

High 

High 

Low 

Low 

High 

S3 

Low 

Low 

Off 

Off 

Off 

Off 

Low 

High 

Driven 

High 

Off 

Off 

Off 

Off 

Off 

S4/S5 

Low 

Low 

Off 

Off 

Off 

Off 

Low 

Off 

Driven 

Off 

Off 

Off 

Off 

Off 

Off 

Description 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

24

Continued to the previous table 

Pin Name 

GPIO23 

GPIO24 

GPIO25 

GPIO26 

GPIO27 

GPIO28 

GPIO29 

GPIO30 

GPIO31 

GPIO32 

GPIO33 

GPIO34 

GPIO35 

GPIO36 

GPIO37 

GPIO38 

GPIO39 

GPIO40 

G[IO41 

GPIO42 

GPIO43 

GPIO[44:47] 

-PCIRST_MSK 

-MPCIACT 

MINI_PD 

-ENABKL_MSK 

--HDD_RST 

-CDROM_RST 

SPK_OFF 

NC 

NC 

NC 

NC 

NC 

NC 

Signal Name 

SSMUXSEL/TP 

-PCLKRUN 

-1394WR 

-GATE1394 


Power Plane 

+3.3VS 

+3.3VS 

+3.3V_ICH 

+3.3V_ICH 

+3.3V_ICH 

+3.3VS 

+3V 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

+3.3VS 

Type 

Plane 

I/O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

Original 

Type 

O 

I/O 

I/O 

I/O 

I/O 

O 

O 

O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 

During 

PCIRST# 

Low 

Low 

High 

High 

High 

High 

High 

High 

High 

High 

High 

Immediately 

after PCIRST# 

MiTac Secret 


Low 

Low 

High 

High 

High 

High 

High 

High 

High 

High 

High 

S1 

High 

High 

High 

High 

Low 

High 

High 

High 

High 

High 

S3 

Off 

Off 

High 

High 

High 

Off 

Off 

Off 

Off 

Off 

Off 

S4/S5 

Off 

Off 

Off 

Off 

Off 

Off 

Off 

Off 

Off 

Off 

Off 

Description 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

not Implement 

25

1.3.8 Keyboard Controller Pin Define 

49 

50 

51 

52 

53 

54 

55 

56 

14 

13 

12 

26~29 

32~35 

1 

7 

8 

10 

11 

20 

21 

Pin 

79~72 

67~60 

82~89 

P40 

P41 

P42 

P43 

P44 

P45 

P46 

P47 

P50 

P51 

P52 

P60~P63 

P64~P67 

STBY 

PA7 

PA6 

PA5 

PA4 

Port 

P10~P17 

P20~P27 

P30~P37 

RESET 

NM# 

KO[0:7] 

SD[0:7] 

H8_SCI 

IRQ1 

IRQ12 

-FAN2 

-FAN1 

PWR_ON 

-H8_RCIN 

KI[0:3] 

KI[4:7] 

-H8_STBY 

T_CLK 

Signal Name 

KO[8:15] 

-CONN_RW 

-H8_WAKE_UP 

-H8_SMI 

LEARNING 

-H8_RESET 

-H8_SUSB 

-ADJ_BTN 

-CONN_STOPEJECT 

H8_PWROK 


Type 

O 

O 

I/O 

I 

O 

O 

O 

O 

O 

O 

O 

O 

O 

O 

I 

I 

I 

I 

I 

I/O 

I 

I 

O 

ICH3M 

ICH3M 

Super I/O 

Super I/O 

FAN2 

FAN1 

Connect To 

Internal Keyboard 


Super I/O 

OZ165 

ICH3M 

DC/DC Connector 

ICH3M 

DD Board 



MAX809 

ICH3M 

Pull-Up 

Touch PAD 

OZ165 

OZ165 

ICH3M 

Keyboard Matrix 


ISA Data Bus 

Audio DJ Scan RW 

Connect to chipset ICH3M to wake up system 

Connect to chipset ICH3M to system management interrupt (Non-ACPI mode) 

Connect to chipset ICH3M to system configuration interrupt (ACPI mode) 

IRQ for Keyboard 

IRQ for Mouse 

Control system fan on & turn on/off duty 

Control CPU fan on & turn on/off duty 

Control system power on/off 

Keyboard reset 

Control DD board voltage, negative logic 



Reset H8-F3437 

STR indicator 

No use 

Connect to Touch Pad clock 

Audio DJ Power Button 

Audio DJ CD-ROM Stop and Eject 

System Power Ready 

Description 

MiTac Secret 


26


30 

31 

47 

48 

57 

58 

68 

69 

80 

81 

90 

91 

5 

6 

16 

17 

18 

10 

22 

23 

24 

25 

99 

Pin 

PA3 

PA2 

PB3 

PB2 

PB1 

PB0 

MD1 

MD0 

P97 

P96 

P95 

P94 

P93 

P92 

P91 

P90 

P86 

Port 

PA1 

PA0 

PB7 

PB6 

PB5 

PB4 

-ADEN 

-CONN_PLAYPAUSE 

T_DATA 

ADJ_ON 

H8_MODE0 

BAT_DATA 

-H8_ICH3BTN 

-PWERBTN 

-LID 

Signal Name 

-BATT_EDAD 

-RI 

-CONN_FF 

CHARGING 

FAN1_SPD 

FAN2_SPD 

LED_DATA 

LED_CLK 

H8_MODE1 

H8_A20GATE 

SW_+5VA 

-H8_THRM 

-H8_SUSC 

BAT_CLK 


Type 

I 

O 

I 

I 

I/O 

I 

I 

O 

I 

I 

O 

O 

I 

I 

I/O 

I 

O 

O 

O 

I 

I 

I 

I/O 

D/D Connector 

OZ165 

FAN1 

FAN2 

Connect To 

Power Circuitry 

LAN/CARD BUS 

Touch PAD 

OZ165 

OZ165 

Charge Circuitry 

74164 

74164 

Pull-Up 

Pull-Up 

BAT_H8 

ICH3M 

ICH3M 

LP-2951 

ICH3M 

Power Button 

LID switch 

ICH3M 

Battery 

Adaptor in 

Audio DJ Play and Pause 

Indicated the battery capacity is not enough to power on system 

If system on suspend mode, then received this signal & system have to wake up 

Connect to Touch Pad DATA 

Control OZ165 Power 

Audio DJ Scan FF 

Indicated charge circuitry to work 

Return FAN1 (CPU FAN) Speed 

Return FAN2 (System FAN) Speed 

(Bit 0-7: -SCROLL, -NUM, -CAP, -AC POWER, -BATT POWER, BATTR, -BATT_G) 

For LED indicated 

H8 Mode select 

H8 Mode select 

SM_BUS DATA for Smart Battery 

For A20M 

Button to ICH3M` 

To switch +5V/+5VA power source 

To ICH3M, Requesting the system to enter power management mode, clock throttling 

System power button 

Cover switch, logic low means LCD cover closed 

System inter S4~S5, positive logic 

SM_BUS clock for Smart Battery 

Description 

MiTac Secret 


27


98 

97 

96 

95 

94 

93 

45 

44 

43 

42 

41 

40 

39 

38 

Pin 

P85 

P84 

P83 

P82 

P81 

P80 

P77 

P76 

P75 

P74 

P73 

P72 

P71 

P70 

Port 

-H8_MCCS 

-IOW 

-IOR 

-H8_KBCS 

SA2 

BLADJ 

CHG_I 

+5VS 

+5V 

+1.8VS 

I_LIMIT 

Signal Name 

H8_A20GATE 

BAT_VOLT 

BAT_TEMP 


Type 

I 

I 

I 

I 

O 

I 

O 

O 

I 

I 

I 

I 

I 

I 

Connect To 

Super I/O 

Super I/O 

Super I/O 

Super I/O 

ICH3M 

Super I/O 

Inverter 

Charger Circuitry 

Charge 

Battery 

Battery 

Port 60h/64h chip select 

Input/Output Write 

Input/Output Red 

Port 62h/66h chip select 

For A20M 

ISA address 

Back/Light adjust control 

+5VS monitor 

+5V monitor 

+1.8VS monitor 

For battery charge 

Report battery voltage 

Report battery thermal 

1.3.9 Power Consumption of Suspend Mode 

Suspend to RAM < 90mA 

Suspend to Disk /Soft-off /Mechanical off < 1.2mA 

Description 

MiTac Secret 


28

29 



N/B Maintenance 

0.975 

0 

0 

0 

0 

1 

0.950 

1 

0 

0 

0 

1 

0.925 

0 

1 

0 

0 

1 

0.900 

1 

1 

0 

0 

1 

0.875 

0 

0 

1 

0 

1 

0.850 

1 

0 

1 

0 

1 

0.825 

0 

1 

1 

0 

1 

0.800 

1 

1 

1 

0 

1 

0.775 

0 

0 

0 

1 

1 

0.750 

1 

0 

0 

1 

1 

0.725 

0 

1 

0 

1 

1 

0.700 

1 

1 

0 

1 

1 

0.675 

0 

0 

1 

1 

1 

0.650 

1 

0 

1 

1 

1 

0.625 

0 

1 

1 

1 

1 

0.600 

1 

1 

1 

1 

1 

Vcc_ 

VID0 

VID1 

VID2 

VID3 

VID4 

Processor Pins 

1.4 Appendix : Voltage Identification Definition 

1.750 

0 

0 

0 

0 

0 

1.700 

1 

0 

0 

0 

0 

1.650 

0 

1 

0 

0 

0 

1.600 

1 

1 

0 

0 

0 

1.550 

0 

0 

1 

0 

0 

1.500 

1 

0 

1 

0 

0 

1.450 

0 

1 

1 

0 

0 

1.400 

1 

1 

1 

0 

0 

1.350 

0 

0 

0 

1 

0 

1.300 

1 

0 

0 

1 

0 

1.250 

0 

1 

0 

1 

0 

1.200 

1 

1 

0 

1 

0 

1.150 

0 

0 

1 

1 

0 

1.100 

1 

0 

1 

1 

0 

1.050 

0 

1 

1 

1 

0 

1.000 

1 

1 

1 

1 

0 

Vcc_ 

VID0 

VID1 

VID2 

VID3 

VID4 

Processor Pins 

MiTac Secret 

Confidential Document

2. System View and Disassembly 

2.1 System View 

2.1.1 Front View 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

Turn Down Button 

Turn Up Button 

Stop/Eject Button 

Play/Pause Button 

Button 

Button 

CD/DVD-ROM Power Button 

External Microphone Jack 

Line Out Phone Jack 

Line Out Phone Jack 

Top Cover Latch 

Hard Disk Drive 

2.1.2 Left-side View 

1 

CD/DVD Disk Drive 


2 4 6 

1 3 5 

7 

8 

9 

10 11 

MiTac Secret 


12 

1 

30

2.1.3 Right-side View 

1 

2 

PCMCIA Card Socket 

IR Sensor 

2.1.4 Rear View 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

Power Connector 

USB Ports 

1394 Jack 

RJ-45 Connector 

Parallel Port 

VGA Port 

System Fan 

S-Video Output Connector 

Kensington Lock 

RJ-11 Connector 

Ventilation Openings 


2 

1 2 

MiTac Secret 


1 3 4 5 6 7 8 9 10 

11 

31

2.1.5 Bottom View 

1 

2 

3 

4 

Wireless Card 

Battery Pack 

Extend SO-DIMM 

Hard Disk Drive 

2.1.6 Top-open View 

1 

2 

3 

4 

5 

6 

7 

8 

9 

Battery Charge Indicator 

Battery Power Indicator 

AC Power Indicator 

Microphone 

Keyboard 

Touch Pad 

LCD Screen 

Device Indicators 

Power Button 


MiTac Secret 


1 

2 

6 

5 

4 

3 

2 

1 

3 

4 

4 

9 

8 

7 

32

2.2 System Disassembly 


The section discusses at length each major component for disassembly/reassembly and show corresponding 

illustrations. Use the chart below to determine the disassembly sequence for removing components from the 

notebook. 

NOTE: 1. Before you start to install/replace these modules, disconnect all peripheral devices and make sure 

the notebook is not turned on or connected to AC power. 

2. During disassembly, 1) Label each cable as you disconnect it, noting its position and routing; 

2) Keep all the screws. 

MiTac Secret 


33

NOTEBOOK 


Modular Components 

LCD Assembly Components 

Base Unit Components 

2.2.1 Battery Pack 

2.2.2 Keyboard 

2.2.3 HDD Module 

2.2.4 CD-ROM Drive 

2.2.5 Wireless Card 

2.2.6 LCD Assembly 

2.2.7 Inverter Board 

2.2.8 LCD Panel 

2.2.9 CPU 

2.2.10 SO-DIMM 

2.2.11 Modem Card 

MiTac Secret 


2.2.12 D/D Board 

2.2.13 System Board 

2.2.14 Audio Board 

2.2.15 Touch Pad Board 

2.2.16 Touch Pad Module 

34

2.2.1 Battery Pack 

Disassembly 


1. Carefully put the notebook upside down. 

2. Slide the release lever to the “unlock” ( ) position (), while take the battery pack out of the compartment (). 

(Figure 2-1) 

Reassembly 

 

 

Figure 2-1 Remove the battery pack 

MiTac Secret 


1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a 

clicking sound. 

2. Slide the release lever to the “lock” ( ) position. 

35

2.2.2 Keyboard 

Disassembly 


1. Remove the battery pack. (See section 2.2.1 Disassembly) 

2. Open the top cover. 

3. Loosen the four latches locking the keyboard. (Figure 2-2) 

Figure 2-2 Loosen the four latches Figure 2-3 Disconnect the cable 

4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard. (Figure 2-3) 

Reassembly 

MiTac Secret 


1. Reconnect the keyboard cable and fit the keyboard back into place with four latches. . 

2. Replace the battery pack. (See section 2.2.1 Reassembly) 

36

2.2.3 HDD Module 

Disassembly 

Figure 2-4 Remove HDD module 


1. Carefully put the notebook upside down. 


3. Remove one screw and slide out the HDD compartment cover. (Figure 2-4) 

4. Slide HDD module out from the compartment carefully. (Figure 2-5) 

Reassembly 

MiTac Secret 


Figure 2-5 Disassemble the hard disk 

1. Slide the HDD module into the compartment , then replace the HDD compartment cover. 


37

2.2.4 CD/DVD-ROM Drive 

Disassembly 

Figure 2-6 Remove one screw 


1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.2.1 Disassembly) 

2. Remove the HDD module. (See section 2.2.3 Disassembly) 

3. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-6) 

4. Insert a small screwdriver or rod through the HDD module’s compartment and push the CD/DVD-ROM to release 

the tray firmly (). Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out (). 

(Figure 2-7) 

Reassembly 

MiTac Secret 


1. Push the CD/DVD-ROM drive into the compartment and secure with one screw. 

2. Replace the HDD module. (See section 2.2.3 Reassembly) 


 

Figure 2-7 Remove the CD/DVD-ROM drive 

 

38

2.2.5 Wireless Card 

Disassembly 


Complete the steps in Section 2.2 to prepare the system for disassembly. 


2. Remove two screws fastening the mini PCI cover. (Figure 2-8) 

3. Disconnect the antenna connecting the wireless card. (Figure 2-9 step 1) 

MiTac Secret 


Figure 2-8 Remove the mini PCI cover Figure 2-9 Remove the antenna 

4. Pull the retaining clips outwards () and remove the wireless card (). (Figure 2-9 step 2) 

1 

2 

39

Reassembly 


1. To install the wireless card, match the wireless card’s notched part with the socket’s projected part and firmly 

insert the card into the socket. Then push down until the retaining clips lock the card into the socket. 

2. Attach the antenna. Then replace the cover and secure with two screws. 

3. Replace the battery pack. (See section 2.2.1Reassembly) 

MiTac Secret 


40

2.2.6 LCD ASSY 

Disassembly 


1. Remove the battery pack and keyboard. (See sections 2.2.1 and 2.2.2 Disassembly) 

2. Carefully upside down the notebook, then remove two screws on the bottom of the notebook. (Figure 2-10) 

3. Disconnect the antenna from the wireless card. (See the step 1, 2 of section 2.2.5 Disassembly) 

4. Turnover the notebook and remove two screws on the rear side of the notebook. (Figure 2-11) 

Figure 2-10 Remove two screws on the 

bottom side of notebook 

MiTac Secret 


Figure 2-11 Remove two screws on the 

rear side of notebook 

41


5. To remove the hinge cover, unscrew three screws. (Figure 2-12) 

6. Disconnect the LCD cables from the mother board () and Pull out the antenna from the KB cable’s compartment 

(). Then unscrew the four screws (). Now you can separate the LCD ASSY. (Figure 2-13) 

Reassembly 

Figure 2-12 Remove the hinge cover Figure 2-13 Remove the LCD ASSY 

MiTac Secret 


1. Attach the LCD assembly to the base unit and secure with four screws on the hinges. 

2. Reconnect the two cables to the mother board. 

3. Reconnect the antenna to the wireless card. (See section 2.2.5 Reassembly) 

4. Replace the hinge cover and secure with three screws. 

5. Replace the keyboard and battery pack. (See sections 2.2.2 and 2.2.1 Reassembly) 

 

 

 

 

 

42

2.2.7 Inverter Board 

Disassembly 


1. Remove the battery pack, keyboard and LCD assembly. (See sections 2.2.1, 2.2.2 and 2.2.6 Disassembly) 

2. Remove six rubber pads and six screws fastening the LCD cover. (Figure 2-14) 

3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the cover out. Repeat the process until 

the cover is completely separated from the housing. . 

4. To remove the inverter board on the lower part of the LCD housing , remove two screws and disconnect two 

cables. (Figure 2-15) 

Reassembly 

MiTac Secret 


Figure 2-14 Remove LCD cover Figure 2-15 Remove the inverter board 

1. Reconnect the cables. Fit the inverter board back into place and secure with two screw. 

2. Replace the LCD cover and secure with six screws and rubber pads. 

3. Replace the LCD assembly, keyboard and battery pack. (See section 2.2.6, 2.2.2 and 2.2.1 Reassembly) 

43

2.2.8 LCD Panel 

Disassembly 


1. Remove the battery pack, keyboard, and LCD assembly. (See sections 2.2.1 to 2.2.2 and 2.2.6 Disassembly) 

2. Remove the LCD cover. (See the step 1 to 3 of section 2.2.7 Disassembly) 

3. Disconnect one cable from the inverter board on the lower part of the panel. (Figure 2-16) 

4. Remove the four screws on two sides of the panel and four screws on the lower part of the LCD panel. (Figure 2-16) 

Reassembly 

Figure 2-16 Remove LCD panel 

MiTac Secret 


1. Fit the LCD panel back into place and secure with eight screws, and reconnect the cable to the inverter board. 

2. Fit the LCD cover back into the housing and ensure inosculated well . Then replace the six screws and six rubber pads. 

3. Replace the LCD assembly, keyboard, battery pack. (See section 2.2.6, 2.2.2 and 2.2.1 Reassembly) 

44

2.2.9 CPU 

Disassembly 


1. Remove the battery pack, keyboard, HDD module, CD/DVD-ROM drive and LCD assembly. (See sections 2.2.1 

to 2.2.6 Disassembly) 

2. Turn the four hex nuts to left to unscrew it completely. (Figure 2-17) 

3. Carefully put the notebook upside down. Remove sixteen screws on the bottom of the notebook. Then detach the 

housing. (Figure 2-18) 

MiTac Secret 


Figure 2-17 Remove the four hex nuts Figure 2-18 Remove the sixteen screws 

45


4. Remove three screws fastening the mother board ASSY. (Figure 2-19) 

5. Disconnect the two speaker cables (); MDC wire (); cover switch cable (); MIC wire (); Audio cable (). 

(Figure 2-20) 

Figure 2-19 Remove the three screws Figure 2-20 Disconnect all the cables and wires 

 

 

 

MiTac Secret 


 

 

 

46


7. Disconnect the TP & MB cable. Now you can separate the system board ASSY. (Figure 2-21) 

8. To remove the heatsink ASSY, remove four spring screws fastening the heatsink ASSY and disconnect the fan’s 

power cord. (Figure 2-22) 

Figure 2-21 Remove the system board 

Figure 2-22 Remove the heatsink ASSY 

MiTac Secret 


47


7. Using a flat screwdriver, rotate the lock of the CPU socket until the arrow points to the “O” position for 

removing the CPU. (Figure 2-23) 

Reassembly 

Figure 2-23 Remove the CPU 

MiTac Secret 


1. Align the arrowhead corner of the CPU with the beveled corner of the socket and insert the CPU pins into holes. 

2. Use a flat screwdriver to rotate the lock of the CPU socket until the arrow points to the “L” position for securing 

the CPU in place. 

3. Reconnect the fan’s power cord to the system board, and fit the heatsink onto the top of the CPU and secure with 

four screws. 

4. Replace the heatsink and secure with four spring screws. Then reconnect the fan’s power cord. 

5. Reconnect the TP & MB cable and then fit the mother board into place. 

48


6. Reconnect the two speaker cables (); MDC wire (); cover switch cable (); MIC wire (); Audio cable (). 

7. Fasten the mother board by three screws. 

8. Replace the housing and secure sixteen screws on the bottom of the notebook and four hex nuts on the rear side of 

notebook. 

9. Fasten the housing by four hex nuts on the rear of the notebook. 

10. Replace the LCD ASSY, CD/DVD-ROM, HDD, keyboard and battery pack. (See section 2.2.6 to 2.2.1 Reassembly) 

MiTac Secret 


49


2.2.10.1 Extend SO-DIMM 

Disassembly 



2. Remove two screws locking the extend SO-DIMM compartment cover. (Figure 2-24) 

3. Full the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-24) 

Figure 2-24 Remove the extend SO-DIMM cover 

Reassembly 

MiTac Secret 


Figure 2-24 Remove the extend SO-DIMM 

1. To install the SO-DIMM, match the SO-DIMM’s notched part with the socket’s projected part and firmly 

insert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the 

SO-DIMM into socket. Then replace the extend SO-DIMM compartment cover and secure with two screws. 

2.Replace the battery pack. (See section 2.2.1 Reassembly) 

50


2.2.10.2 Extend SO-DIMM 

Disassembly 

Figure 2-25 Remove the SO-DIMM 


1. Remove the mother board ASSY. (See the step 1 to 7of section 2.2.1 Disassembly) 

2. Full the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-25) 

Reassembly 

Figure 2-25 Remove the SO-DIMM 

MiTac Secret 


1. To install the SO-DIMM, match the SO-DIMM’s notched part with the socket’s projected part and firmly 

insert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the 

SO-DIMM into cover. 

2. Assemble the notebook. 

51

2.2.11 Modem Card 

Disassembly 





3. Remove two screw fastening the modem card. (Figure 2-26) 

4. Then disconnect the cable from the modem card. (Figure 2-27) 

Reassembly 

Figure 2-26 Remove two screws 

1. Reconnect the cable to the modem card and secure the modem card with two screw. 

2. Assemble the notebook. (See previous sections Reassembly) 

Figure 2-27 Disconnect the MDM cable 

MiTac Secret 


52

2.2.12 D/D Board 

Disassembly 





3. Rock the D/D board to detach from the mother board. (Figure 2-28) 

Reassembly 

Figure 2-28 Detach the D/D Board 

MiTac Secret 


1. Insert the D/D board’s pins into the connector. Then push it down and ensure every pin insert well. 


53

2.2.13 Mother Board 

Disassembly 




2. Remove the heatsink, CPU, SO-DIMM, modem card, D/D board. (See section 2.2.9 to 2.2.12 Disassembly) 

3. Rock the D/D board to detach from the mother board. (Figure 2-29) 

Reassembly 

Figure 2-29 Detach the mother Board 

MiTac Secret 


1. Replace the D/D Board, modem card, CPU, heatsink. (See section 2.2.12 to 2.2.9 Reassembly) 


54

2.2.14 Audio Board 

Disassembly 





3. Remove two screws fastening the audio board and release the cable. (Figure 2-30, 2-31) 

Reassembly 

MiTac Secret 


Figure 2-30 Remove the audio board Figure 2-31 Disconnect the cable 

1. Reconnect the cables to the audio board. 

2. Replace the audio board and secure with two screws. 


55

2.2.15 Touch Pad Board 

Disassembly 





3. Remove the audio board. (See section 2.2.13 Disassembly) 

4. Remove the three screws to lift up the touch pad board. (Figure 2-31) 

5. Disconnect the TP & MB and the touch pad cables. (Figure 2-32) 

Reassembly 

MiTac Secret 


Figure 2-32 Remove the touch pad board Figure 2-33 Disconnect two cables 

1. Reconnect the TP & MB and the touch pad cables to the board 

2. Replace the touch pad board and secure with three screws. 


56

2.2.16 Touch Pad Module 

Disassembly 





3. Remove the audio board and touch pad board. (See sections 2.2.13 and 2.2.14 Disassembly) 

4. Remove four screws fastening the the touch pad module and disconnect the touch pad’s cable to lift up the touch 

pad module. (Figure 2-33) 

Reassembly 

MiTac Secret 


Figure 2-34 Remove the top mother board 

1. Replace the touch pad module and bracket and secure with four screws. 

2. Reconnect the cables to the board. 


57

3.1 Main Board (Side A) – 1 


3. Definition & Location of Connectors / Switches 

J3 

J2 

J4 

J5 

J6 

J7 

J9 

J8 

J11 

J23 

J10 

J21 

J22 

J15 

J12 

J16 J19 

J17 

J20 

J13 

J18 

U19 

J2, J22 : FAN Connector 

J3 : RJ11 Connector 

J4 : LCD Connector 

J5 : Secondary EIDE Connector 

J6 : S-Video Connector 

J7 : Primary EIDE Connector 

J8 : External VGA Connector 

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J9 : DC to DC Board Connector 

J10 : Parallel Port Connector 

J11 : DDR SO-DIMM Module Socket 

J12 : LAN (RJ45) Connector 

------ To next page ------ 

58

3.1 Main Board (Side A) – 2 


3. Definition & Location of Connectors/ Switches 

J3 

J2 

J4 

J5 

J6 

J7 

J9 

J8 

J11 

J10 

J21 

J22 

J15 

J12 

J16 J19 

J17 

J20 

J13 

J18 

U19 

------ Continued to previous page ------ 

J13 : PCMCIA Card Bus Socket 

J15 : Internal Keyboard Connector 

J16 : IEEE1394 Connector 

J17 : USB Port Connector 

J18 : Battery Connector 

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J23 

J20 : Modem Daughter Board (MDC) Connector 

J21 : RTC Battery Connector 

J23 : Touch-pad Connector 

U19 : FIR Module 

59

3.1 Main Board (Side B) 


3. Definition & Location of Connectors/ Switches 

J508 

J507 J506 

J13 

J505 

J502 

J501 

J503 

J501 : Left Internal Speaker Connector 

J502 : DDR SO-DIMM Module Socket 

J503 : MDC Jump Wire Connector 

J505 : Internal Microphone Connector 

J506 : Audio DJ Board Connector 

J507 : Mini PCI Socket 

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J508 : Right Internal Speaker Connector 

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3.2 Audio DJ Board 



SW507 SW501 SW502 SW503 SW504 SW505 SW506 

J1 

Side A 

Side B 

J501 

J502 

J502 

J503 

SW501 : Volume Up Switch 

SW502 : STOP/EJECT Switch 

SW503 : PLAY/PAUSE Switch 

SW504 : FF Switch 

SW505 : RW Switch 

SW506 : ADJ Button 

SW507 : Volume Down 

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J501 : External Microphone Jack 

J502 : Line In Jack 

J503 : Line Out Jack 

J1 : Audio DJ Board Connector 

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3.3 DC to DC Board 



SW1 

J2 

Side A 

PU501 

Side B 

PU4 

J502 

J502 : DC to DC Board Connector 

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PU501 : LTC3707 (DDR_2.5V) DC to DC Converter 

J2 : Inverter Board Connector 

SW1 : Power Switch 

PU4 : CM8500 (REF_1.25V) DC to DC Converter 

62

4.1 Main Board (Side A) 


4. Definition & Location of Major Components 

U1 

PU5 

U3 

U4 

U5 

U6 

U7 

U14 

U1 : Intel Mobile Pentium4 (Northwood-M) 

Processor 

U3 : Intel 82845 Memory Controller Hub 

(MCH-M) 

U4 : NVIDIA NV17-MAP VGA Controller 

U5 : ICS950805 Clock Generator 

U6 : RTL8139CL LAN Controller 

U7 : PH163112 LAN Buffer 

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U18 

U14 : ALC202 Audio CODEC 

U17 : PCI4410 PCMCIA Controller 

U18 : VT6202 USB2.0 Hub 

PU5 : LTC3716 CPU_CORE DC to DC Converter 

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4.1 Main Board (Side B) 


4. Definition & Location of Major Components 

PU507 

U518 

J13 

U517 

U515 

U508 

U510 

U511 

U505 

U505 : OZ165 Audio DJ Controller 

U508 : Intel 82801CAM I/O Controller Hub 

(ICH3-M) 

U510 : Flash ROM (BIOS) 

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U511 : PC87393 Super I/O Controller 

U515 : TSB41AB1 IEEE1394 Controller 

U517 : H8/F3437 Micro Controller 

U518 : SN74CBTD3384 Level Shift 

PU507 : MAX1632 System Power (3V, 5V, +12V) 

DC to DC Converter 

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5. Pin Descriptions of Major Components 

5.1 Intel Mobile Pentium 4 Processor – M 

Signal Name Type Description 

A[35:3]# Input/ A[35:3]# (Address) define a 2 36 -byte physical memory address space. 

Output In sub-phase 1 of the address phase, these pins transmit the address of a 

transaction. In sub-phase 2, these pins transmit transaction type 

information. These signals must connect the appropriate pins of all 

agents on the Mobile Intel Pentium 4 Processor-M system bus. A[35:3]# 

are protected by parity signals AP[1:0]#. 

A[35:3]# are source synchronous signals and are latched into the 

receiving buffers by ADSTB[1:0]#. 

On the active-to-inactive transition of RESET#, the processor samples a 

subset of the A[35:3]# pins to determine power-on configuration. 

A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks physical 

address bit 20 (A20#) before looking up a line in any internal cache and 

before driving a read/ write transaction on the bus. Asserting A20M# 

emulates the 8086 processor's address wrap-around at the 1-Mbyte 

boundary. Assertion of A20M# is only supported in real mode. 

A20M# is an asynchronous signal. However, to ensure recognition of 

this signal following an Input/Output write instruction, it must be valid 

along with the TRDY# assertion of the corresponding Input/Output 

Write bus transaction. 

ADS# Input/ ADS# (Address Strobe) is asserted to indicate the validity of the 

Output transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents 

observe the ADS# activation to begin parity checking, protocol 

checking, address decode, internal snoop, or deferred reply ID match 

operations associated with the new transaction. 

ADSTB[1:0]# Input/ Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising 

Output and falling edges. Strobes are associated with signals as shown below. 

Signals Associated Strobe 

REQ[4:0]#, a[16:3]# ADSTB0# 

A[35:17#] ADSTB1# 

AP[1:0]# Input/ AP[1:0]# (Address Parity) are driven by the request initiator along with 

Output ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct 

parity signal is high if an even number of covered signals are low and 

low if an odd number of covered signals are low. This allows parity to be 

high when all the covered signals are high. AP[1:0]# should connect the 

appropriate pins of all Mobile Intel Pentium 4 Processor-M system bus 

agents. The following table defines the coverage model of these signals. 

Request Signals subphase 1 subphase 2 

A[35:24]# AP0# AP1# 

A[23:3#] AP1# AP0# 

REQ[4:0]# AP1# AP0# 

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BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the system bus 

frequency. All processor system bus agents must receive these signals to 

drive their outputs and latch their inputs. 

All external timing parameters are specified with respect to the rising 

edge of BCLK0 crossing VCROSS . 

BINIT# Input/ BINIT# (Bus Initialization) may be observed and driven by all processor 

Output system bus agents and if used, must connect the appropriate pins of all 

such agents. If the BINIT# driver is enabled during power-on 

configuration, BINIT# is asserted to signal any bus condition that 

prevents reliable future operation. 

If BINIT# observation is enabled during power-on configuration, and 

BINIT# is sampled asserted, symmetric agents reset their bus LOCK# 

activity and bus request arbitration state machines. The bus agents do not 

reset their IOQ and transaction tracking state machines upon observation 

of BINIT# activation. Once the BINIT# assertion has been observed, the 

bus agents will re-arbitrate for the system bus and attempt completion of 

their bus queue and IOQ entries. 

If BINIT# observation is disabled during power-on configuration, a 

central agent may handle an assertion of BINIT# as appropriate to the 

error handling architecture of the system. 

BNR# Input/ BNR# (Block Next Request) is used to assert a bus stall by any bus agent 

Output who is unable to accept new bus transactions. During a bus stall, the 

current bus owner cannot issue any new transactions. 

BPM[5:0]# Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance 

Output monitor signals. They are outputs from the processor which indicate the 

status of breakpoints and programmable counters used for monitoring 

processor performance. BPM[5:0]# should connect the appropriate pins 

of all Mobile Intel Pentium 4 Processor-M system bus agents. 

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. 

PRDY# is a processor output used by debug tools to determine processor 

debug readiness. 

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. 

PREQ# is used by debug tools to request debug operation of the 

processor. 

These signals do not have on-die termination and must be 

terminated on the system board. 

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BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the 

processor system bus. It must connect the appropriate pins of all 

processor system bus agents. Observing BPRI# active (as asserted by the 

priority agent) causes all other agents to stop issuing new requests, 

unless such requests are part of an ongoing locked operation. The 

priority agent keeps BPRI# asserted until all of its requests are 

BR0# Input/ 

Output 

completed, then releases the bus by deasserting BPRI#. 

BR0# drives the BREQ0# signal in the system and is used by the 

processor to request the bus. During power-on configuration this pin is 

sampled to determine the agent ID = 0. 

This signal does not have on-die termination and must be 

terminated. 

BSEL[1:0] Output BSEL[1:0] (Bus Select) are used to select the processor input clock 

frequency. The required frequency is determined by the processor, 

chipset and clock synthesizer. All agents must operate at the same 

frequency. The Mobile Intel Pentium 4 Processor-M operates at a 400 

MHz system bus frequency (100 MHz BCLK[1:0] frequency). 

COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision 

D[63:0]# Input/ 

Output 

resistors. 

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data 

path between the processor system bus agents, and must connect the 

appropriate pins on all such agents. The data driver asserts DRDY# to 

indicate a valid data transfer. 

D[63:0]# are quad-pumped signals and will thus be driven four times in 

a common clock period. D[63:0]# are latched off the falling edge of both 

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals 

correspond to a pair of one DSTBP# and one DSTBN#. The following 

table shows the grouping of data signals to data strobes and DBI#. 

Quad-Pumped Signal Groups 

Data Group DSTBN#/DSTBP# DBI# 

D[15:0]# 0 0 

D[31:16]# 1 1 

D[47:32]# 2 2 

D[63:48]# 3 3 

DBR# 

Furthermore, the DBI# pins determine the polarity of the data signals. 

Each group of 16 data signals corresponds to one DBI# signal. When the 

DBI# signal is active, the corresponding data group is inverted and 

therefore sampled active high. 

Output DBR# (Data Bus Reset) is used only in processor systems where no 

debug port is implemented on the system board. DBR# is used by a 

debug port interposer so that an in-target probe can drive system reset. If 

a debug port is implemented in the system, DBR# is a no connect in the 

system. DBR# is not a processor signal. 


DBI[3:0]# Input/ 

Output 

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the 

polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated 

when the data on the data bus is inverted. The bus agent will invert the 

data bus signals if more than half the 

bits, within the covered group, would change level in the next cycle. 

DBI[3:0] Assignment To Data Bus 

Bus Signal Data Bus Signals 

DBI3# D[63:48]# 

DBI2# D[47:32]# 

DBI1 D[31:16]# 

DBI0 D[15:0]# 

DBSY# Input/ DBSY# (Data Bus Busy) is asserted by the agent responsible for driving 

Output data on the processor system bus to indicate that the data bus is in use. 

The data bus is released after DBSY# is deasserted. This signal must 

connect the appropriate pins on all processor system bus agents. 

DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be 

guaranteed in-order completion. Assertion of DEFER# is normally the 

responsibility of the addressed memory or Input/Output agent. This 

signal must connect the appropriate pins of all processor system bus 

agents. 

DP[3:0]# Input/ DP[3:0]# (Data parity) provide parity protection for the D[63:0]# 

Output signals. They are driven by the agent responsible for driving D[63:0]#, 

and must connect the appropriate pins of all Mobile Intel Pentium 4 

Processor-M system bus agents. 

DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition 

from the Sleep State to the Deep Sleep state. In order to return to the 

Sleep State, DPSLP# must be deasserted and BCLK[1:0] must be 

running. 

DRDY# Input/ DRDY# (Data Ready) is asserted by the data driver on each data 

Output transfer, indicating valid data on the data bus. In a multi-common clock 

data transfer, DRDY# may be deasserted to insert idle clocks. This signal 

must connect the appropriate pins of all processor system bus agents. 

DSTBN[3:0]# Input/ Data strobe used to latch in D[63:0]#. 

Output Signal Associated Strobe 

D[15:0], DBI0# DSTBN0# 

D[31:16]#, DBI1# DSTBN1# 

D[47:32]#, DBI2# DSTBN2# 

D[63:48]#, DBI3# DSTBN3# 

GTLREF Input GTLREF determines the signal reference level for AGTL+ input pins. 

GTLREF should be set at 2/3 Vcc. GTLREF is used by the AGTL+ 

receivers to determine if a signal is a logical 0 or logical 1. 

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DSTBP[3:0]# Input/ Data strobe used to latch in D[63:0]#. 

Output Signal Associated Strobe 

D[15:0], DBI0# DSTBP0# 

D[31:16]#, DBI1# DSTBP1# 

D[47:32]#, DBI2# DSTBP2# 

D[63:48]#, DBI3# DSTBP3# 

FERR#/PBE# Output FERR#/PBE# (floating point error/pending break event) is a multiplexed 

signal and its meaning is qualified by STPCLK#. When STPCLK# is not 

asserted, FERR#/PBE# indicates a floating-point error and will be 

asserted when the processor detects an unmasked floating-point error. 

When STPCLK# is not asserted, FERR#/PBE# is similar to the 

ERROR# signal on the INTEL 387 coprocessor, and is included for 

compatibility with systems using MS-DOS*-type floating-point error 

reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# 

indicates that the processor has a pending break event waiting for 

service. The assertion of FERR#/PBE# indicates that the processor 

should be returned to the Normal state. When FERR#/PBE# is asserted, 

indicating a break event, it will remain asserted until STPCLK# is 

deasserted. 

GHI# Input The GHI# signal controls the selection of the operating mode bus ratio 

and voltage in the Mobile Intel Pentium 4 Processor-M. On the Mobile 

Intel Pentium 4 Processor-M featuring Enhanced Intel SpeedStep 

technology, this signal is latched on entry to Sleep state and is observed 

during the Deep Sleep state. GHI# determines which of two performance 

states is selected for operation. This signal is ignored when the processor 

is not in the Deep Sleep state. This signal should be driven with an 

Open-drain driver. . . . 

HIT# 

Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop 

Output operation results. Any system bus agent may assert both HIT# and 

HITM# 

Input/ HITM# together to indicate that it requires a snoop stall, which can be 

Output continued by reasserting HIT# and HITM# together. 

IERR# Output IERR# (Internal Error) is asserted by a processor as the result of an 

internal error. Assertion of IERR# is usually accompanied by a 

SHUTDOWN transaction on the processor system bus. This transaction 

may optionally be converted to an external error signal (e.g., NMI) by 

system core logic. The processor will keep IERR# asserted until the 

assertion of RESET#. 

This signal does not have on-die termination and must be terminated 

on the system board. 

ITPCLKOUT[1:0] Output ITPCLKOUT[1:0] is an uncompensated differential clock output that is a 

delayed copy of the BCLK[1:0], which is an input to the processor. This 

clock output can be used as the differential clock into the ITP port that is 

designed onto the motherboard. If ITPCLKOUT[1:0] outputs are not 

used, they must be terminated properly. 

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IGNNE# Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to 

ignore a numeric error and continue to execute non-control floating-point 

instructions. If IGNNE# is deasserted, the processor generates an 

exception on a non-control floating-point instruction if a previous 

floating-point instruction caused an error. IGNNE# has no effect when 

the NE bit in control register 0 (CR0) is set. 

IGNNE# is an asynchronous signal. However, to ensure recognition of 

this signal following an Input/Output write instruction, it must be valid 

along with the TRDY# assertion of the corresponding Input/Output 

Write bus transaction. 

INIT# Input INIT# (Initialization), when asserted, resets integer registers inside the 

processor without affecting its internal caches or floating-point registers. 

The processor then begins execution at the power-on Reset vector 

configured during power-on configuration. The processor continues to 

handle snoop requests during INIT# assertion. INIT# is an asynchronous 

signal and must connect the appropriate pins of all processor system bus 

agents. 

If INIT# is sampled active on the active to inactive transition of 

RESET#, then the processor executes its Built-in Self-Test (BIST). 

ITP_CLK[1:0] Input ITP_CLK[1:0] are copies of BCLK that are used only in processor 

systems where no debug port is implemented on the system board. 

ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port 

implemented on an interposer. If a debug port is implemented in the 

system, ITP_CLK[1:0] are no connects in the system. 

These are not processor signals. 

LINT[1:0] Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of 

all APIC Bus agents. When the APIC is disabled, the LINT0 signal 

becomes INTR, a maskable interrupt request signal, and LINT1 becomes 

NMI, a nonmaskable interrupt. INTR and NMI are backward compatible 

with the signals of those names on the Pentium processor. Both signals 

are asynchronous. 

Both of these signals must be software configured via BIOS 

programming of the APIC register space to be used either as NMI/INTR 

or LINT[1:0]. Because the APIC is enabled by default after Reset, 

LOCK# Input/ 

Output 

operation of these pins as LINT[1:0] is the default configuration. 

LOCK# indicates to the system that a transaction must occur atomically. 

This signal must connect the appropriate pins of all processor system bus 

agents. For a locked sequence of transactions, LOCK# is asserted from 

the beginning of the first transaction to the end of the last transaction. 

When the priority agent asserts BPRI# to arbitrate for ownership of the 

processor system bus, it will wait until it observes LOCK# deasserted. 

This enables symmetric agents to retain ownership of the processor 

system bus throughout the bus locked operation and ensure the atomicity 

of lock. 

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MCERR# Input/ MCERR# (Machine Check Error) is asserted to indicate an 

Output unrecoverable error without a bus protocol violation. It may be driven by 

all processor system bus agents. 

MCERR# assertion conditions are configurable at a system level. 

Assertion options are defined by the following options: 

Enabled or disabled. 

Asserted, if configured, for internal errors along with IERR#. 

Asserted, if configured, by the request initiator of a bus transaction after 

it observes an error. 

Asserted by any bus agent when it observes an error in a bus transaction. 

PROCHOT# Output The assertion of PROCHOT# (Processor Hot) indicates that the 

processor die temperature has reached its thermal limit. 

PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor requires 

this signal to be a clean indication that the clocks and power supplies are 

stable and within their specifications. ‘Clean’ implies that the signal will 

remain low (capable of sinking leakage current), without glitches, from 

the time that the power supplies are turned on until they come within 

specification. The signal must then transition monotonically to a high 

state. 

The PWRGOOD signal must be supplied to the processor; it is used to 

protect internal circuits against voltage sequencing issues. It should be 

driven high throughout boundary scan operation. 

REQ[4:0]# Input/ REQ[4:0]# (Request Command) must connect the appropriate pins of all 

Output processor system bus agents. They are asserted by the current bus owner 

to define the currently active transaction type. These signals are source 

synchronous to ADSTB0#. 

RESET# Input Asserting the RESET# signal resets the processor to a known state and 

invalidates its internal caches without writing back any of their contents. 

For a power-on Reset, RESET# must stay active for at least one 

millisecond after VCC and BCLK have reached their proper 

specifications. On observing active RESET#, all system bus agents will 

deassert their outputs within two clocks. RESET# must not be kept 

asserted for more than 10 ms while PWRGOOD is asserted. 

A number of bus signals are sampled at the active-to-inactive transition 

of RESET# for power-on configuration. 

This signal does not have on-die termination and must be terminated 

on the system board. 

RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent 

responsible for completion of the current transaction), and must connect 

the appropriate pins of all processor system bus agents. 

SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. 

System board designers may use this pin to determine if the processor is 

present. 

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RSP# Input RSP# (Response Parity) is driven by the response agent (the agent 

responsible for completion of the current transaction) during assertion of 

RS[2:0]#, the signals for which RSP# provides parity protection. It must 

connect to the appropriate pins of all processor system bus agents. 

A correct parity signal is high if an even number of covered signals are 

low and low if an odd number of covered signals are low. While 

RS[2:0]# = 000, RSP# is also high, since this indicates it is not being 

driven by any agent guaranteeing correct parity. 

SMI# Input SMI# (System Management Interrupt) is asserted asynchronously by 

system logic. On accepting a System Management Interrupt, the 

processor saves the current state and enter System Management Mode 

(SMM). An SMI Acknowledge transaction is issued, and the processor 

begins program execution from the SMM handler. 

If SMI# is asserted during the deassertion of RESET# the processor will 

tristate its outputs. 

SLP# Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to 

enter the Sleep state. During Sleep state, the processor stops providing 

internal clock signals to all units, leaving only the Phase-Locked Loop 

(PLL) still operating. Processors in this state will not recognize snoops 

or interrupts. The processor will only recognize the assertion of the 

RESET# signal, deassertion of SLP#, and assertion of DPSLP# input 

while in Sleep state. If SLP# is deasserted, the processor exits Sleep state 

and returns to Stop-Grant state, restarting its internal clock signals to the 

bus and processor core units. If the BCLK input is stopped or if DPSLP# 

is asserted while in the Sleep state, the processor will exit the Sleep state 

and transition to the Deep Sleep state. 

STPCLK# Input Assertion of STPCLK# (Stop Clock) causes the processor to enter a low 

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge 

transaction, and stops providing internal clock signals to all processor 

core units except the system bus and APIC units. The processor 

continues to snoop bus transactions and service interrupts while in 

Stop-Grant state. When STPCLK# is deasserted, the processor restarts its 

internal clock to all units and resumes execution. The assertion of 

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous 

input. 

TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus 

(also known as the Test Access Port). 

TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI 

provides the serial input needed for JTAG specification support. 

TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO 

TESTHI[10:8] 

TESTHI[5:0] 

provides the serial output needed for JTAG specification support. 

Input TESTHI[10:8] and TESTHI[5:0] must be connected to a V CC power 

source through a resistor for proper processor operation. 

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THERMDA Other Thermal Diode Anode. 

THERMDC Other Thermal Diode Cathode. 

THERMTRIP# Output Assertion of THERMTRIP# (Thermal Trip) indicates the processor 

junction temperature has reached a level beyond which permanent 

silicon damage may occur. Measurement of the temperature is 

accomplished through an internal thermal sensor which is configured to 

trip at approximately 135°C. Upon assertion of THERMTRIP#, the 

processor will shut off its internal clocks (thus halting program 

execution) in an attempt to reduce the processor junction temperature. To 

protect the processor, its core voltage (Vcc) must be removed following 

the assertion of THERMTRIP#. Once activated, THERMTRIP# remains 

latched until RESET# is asserted. While the assertion of the RESET# 

signal will deassert THERMTRIP#, if the processor’s junction 

temperature remains at or above the trip level, THERMTRIP# will again 

be asserted. 

TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by 

debug tools. 

TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is 

ready to receive a write or implicit writeback data transfer. TRDY# must 

connect the appropriate pins of all system bus agents. 

TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# 

must be driven low during power on Reset. This can be done with a 680 

ohm pull-down resistor. 

VCCA Input VCCA provides isolated power for the internal processor core PLL’s. 

VCCIOPLL Input VCCIOPLL provides isolated power for internal processor system bus 

PLL’s. . 

VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor core 

power (VCC ). It can be used to sense or measure power near the silicon 

with little noise. 

VCCVID Input Independent 1.2-V supply must be routed to VCCVID pin for the Mobile 

Intel Pentium 4 Processor-M’s Voltage Identification circuit. 

VID[4:0] Output VID[4:0] (Voltage ID) pins are used to support automatic selection of 

power supply voltages (Vcc). Unlike some previous generations of 

processors, these are open drain signals that are driven by the Mobile 

Intel Pentium 4 Processor-M and must be pulled up to 3.3V (max.) with 

1Kohm resistors. The voltage supply for these pins must be valid before 

the VR can supply Vcc to the processor. Conversely, the VR output must 

be disabled until the voltage supply for the VID pins becomes valid. The 

VID pins are needed to support the processor voltage specification 

variations. The VR must supply the voltage that is requested by the pins, 

or disable itself. 

VSSA Input VSSA is the isolated ground for internal PLLs. 

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5.2 Intel 82845 Memory Controller Hub Mobile (MCH-M) 

Host Interface Signals 


ADS# I/O Address Strobe: The system bus owner asserts ADS# to indicate 

AGTL+ the first of two cycles of a request phase. 

BNR# I/O Block Next Request: Used to block the current request bus owner 

AGTL+ from issuing a new request. This signal is used to dynamically 

control the system bus pipeline depth. 

BPRI# O Bus Priority Request: The MCH-M is the only Priority Agent on 

AGTL+ the system bus. It asserts this signal to obtain the ownership of the 

address bus. This signal has priority over symmetric bus requests 

and will cause the current symmetric owner to stop issuing new 

transactions unless the HLOCK# signal was asserted. 

BR0# I/O Bus Request 0#: The MCH-M pulls the processor bus’ BR0# signal 

AGTL+ low during CPURST#. The signal is sampled by the processor on 

the active-to-inactive transition of CPURST#. The minimum setup 

time for this signal is 4 HCLKs. The minimum hold time is 2 clocks 

and the maximum hold time is 20 HCLKs. BR0# should be tristated 

after the hold time requirement has been satisfied. 

CPURST# O CPU Reset: The CPURST# pin is an output from the MCH-M. The 

AGTL+ MCH-M asserts CPURST# while RSTIN# (PCIRST# from 

ICH3-M) is asserted and for approximately 1 ms after RSTIN# is 

deasserted. The CPURST# allows the processor’s to begin 

execution in a known state. 

DBSY# I/O Data Bus Busy: Used by the data bus owner to hold the data bus for 

AGTL+ transfers requiring more than one cycle. 

DEFER# O Defer Response: Signals that the MCH-M will terminate the 

AGTL+ transaction currently being snooped with either a deferred response 

or with a retry response. 

DBI[3:0]# I/O Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. 

AGTL+ 4x Indicates if the associated signals are inverted or not. DBI[3:0]# are 

asserted such that the number of data bits driven electrically low 

(low voltage) within the corresponding 16-bit group never exceeds 

8. 

DBI[x]# Data Bits 

DBI3# HD[63:48]# 

DBI2# HD[47:32]# 

DBI1# HD[31:16]# 

DBI0# HD[15:0]# 

DRDY# I/O 

AGTL+ 

Data Ready: Asserted for each cycle that data is transferred. 

HA[31:3]# I/O Host Address Bus: HA[31:3]# connect to the system address bus. 

AGTL+ 2x During processor cycles the HA[31:3]# are inputs. The MCH-M 

drives HA[31:3]# during snoop cycles on behalf of hub interface 

and AGP/Secondary PCI initiators. HA[31:3]# are transferred at 2x 

rate. Note that the address is inverted on the system bus. 

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HADSTB[1:0]# I/O Host Address Strobe: The source synchronous strobes used to 

AGTL+ 2x transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. 

Strobe Address Bits 

HADSTB0# HA[16:3]#, HREQ[4:0]# 

HADSTB1# HA[31:17]# 

HD[63:0]# I/O Host Data: These signals are connected to the system data bus. 

AGTL+ 4x HD[63:0]# are transferred at 4x rate. Note that the data signals are 

inverted on the system bus. 

HDSTBP[3:0]# I/O Differential Host Data Strobes: The differential source 

HDSTBN[3:0]# AGTL+ 4x synchronous strobes used to transfer HD[63:0]# and DBI[3:0]# at 

the 4x transfer rate. 

Strobe Data Bits 

HDSTBP3#, HDSTBN3# HD[63:48]#, DBI3# 




HIT# I/O Hit: Indicates that a caching agent holds an unmodified version of 

AGTL+ the requested line. Also, driven in conjunction with HITM# by the 

target to extend the snoop window. 

HITM# I/O Hit Modified: Indicates that a caching agent holds a modified 

AGTL+ version of the requested line and that this agent assumes 

responsibility for providing the line. 

Also, driven in conjunction with HIT# to extend the snoop window. 

HLOCK# I Host Lock: All system bus cycles sampled with the assertion of 

AGTL+ HLOCK# and ADS#, until the negation of HLOCK# must be 

atomic, i.e. no hub interface or AGP snoopable access to DRAM 

are allowed when HLOCK# is asserted by the processor. 

HREQ[4:0]# I/O Host Request Command: Defines the attributes of the request. In 

AGTL+ 2x Enhanced Mode HREQ[4:0]# are transferred at 2x rate. Asserted 

by the requesting agent during both halves of Request Phase. In the 

first half the signals define the transaction type to a level of detail 

that is sufficient to begin a snoop request. In the second half the 

signals carry additional information to define the complete 

transaction type. 

HTRDY# O Host Target Ready: Indicates that the target of the processor 

AGTL+ transaction is able to enter the data transfer phase. 

70



Host Interface Signals (Continued) 


RS[2:0]# O 

AGTL+ 

Response Status: Indicates type of response according to the 

following the table: 

RS[2:0] Response type 

000 Idle state 

001 Retry response 

010 Deferred response 

011 Reserved (not driven by MCH-M) 

100 Hard Failure (not driven by MCH-M) 

101 No data response 

110 Implicit Write back 

111 Normal data response 

DDR Interface Signals 


SCS#[3:0] O 

CMOS 

SMA[12:0] O 

CMOS 

SBS[1:0] O 

CMOS 

SRAS# O 

CMOS 

SCAS# O 

CMOS 

SWE# I/O 

CMOS 

Chip Select: These pins select the particular DDR components 

during the active state. 

Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM 

device row. These signals can be toggled on every rising System 

Memory Clock edge. 

Multiplexed Memory Address: These signals are used to provide 

the multiplexed row and column address to DDR. 

Memory Bank Address: These signals define the banks that are 

selected within each DDR row. The SMA and SBS signals combine 

to address every possible location within a DDR device. 

DDR Row Address Strobe: SRAS# may be heavily loaded and 

requires 2 DDR clock cycles for setup time to the DDRs: Used with 

SCAS# and SWE# (along with SCS#) to define the DRAM 

commands. 

DDR Column Address Strobe: SCAS# may be heavily loaded and 

requires 2 DDR clock cycles for setup time to the DDRs. Used with 

SRAS# and SWE# (along with SCS#) to define the DRAM 

commands. 

Write Enable: Used with SCAS# and SRAS# (along with SCS#) to 

define the DRAM commands. SWE# is asserted during writes to 

DDR. SWE# may be heavily loaded and requires 2 DDR clock 

cycles for setup time to the DDRs. 

Data Lines: These signals are used to interface to the DDR data 

SDQ[63:0] I/O 

CMOS 2X bus. 

SCB[7:0] I/O Data Lines: These signals are used to interface to the SDRAM ECC 

CMOS 2X signals (to be used if SO-DIMMs support ECC). 


SDQS[8:0] I/O 

CMOS 

SCKE[3:0] O 

CMOS 

RCVENOUT# O 

CMOS 

RCVENIN# I 

CMOS 

Data Strobes: 

There is an associated data strobe (DQS) for each data strobe 

(DQ) and check bit (CB) group. 

SDQS8 -> SCB[7:0] 

SDQS7 -> SDQ[63:56] 

SDQS6 -> SDQ[55:48] 

SDQS5 -> SDQ[47:40] 

SDQS4 -> SDQ[39:32] 

SDQS3 -> SDQ[31:24] 

SDQS2 -> SDQ[23:16] 

SDQS1 -> SDQ[15:8] 

SDQS0 -> SDQ[7:0] 

Clock Enable: These pins are used to signal a self-refresh or power 

down command to a DDR array when entering system suspend. 

SCKE is also used to dynamically power down inactive DDR rows. 

There is one SCKE per DDR row. 

These signals can be toggled on every rising SCLK edge. 

Clock Output: Used to emulate source-synch clocking for reads. 

Connects to RCVENIN#. 

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Clock Input: Used to emulate source-synch clocking for reads. 

Connects to RCVENOUT#. 

Hub Interface Signals 


HI_[10:0] I/O 

CMOS 

Hub Interface Signals: Signals used for the hub interface. 

HI_STB I/O Hub Interface Strobe: One of two differential strobe signals used 

CMOS 

HI_STB# I/O 

CMOS 

to transmit or receive packet data over hub interface. 

Hub Interface Strobe Compliment: One of two differential strobe 

signals used to transmit or receive packet data over hub interface. 

71



AGP Addressing Signals 


PIPE# I 

AGP 

SBA[7:0] I 

AGP 

Pipelined Read: This signal is asserted by the AGP master to 

indicate a full width address is to be enqueued on by the target using 

the AD bus. One address is placed in the AGP request queue on 

each rising clock edge while PIPE# is asserted. When PIPE# is 

deasserted no new requests are queued across the AD bus. 

During SBA Operation: This signal is not used if SBA (Side Band 

Addressing) is selected. 

During FRAME# Operation: This signal is not used during AGP 

FRAME# operation. 

PIPE# is a sustained tri-state signal from the AGP masters 

(graphics controller) and is an MCH-M input. 

Side-band Address: These signals are used by the AGP master 

(graphics controller) to place addresses into the AGP request queue. 

The SBA bus and AD bus operate independently. That is, 

transaction can proceed on the SBA bus and the AD bus 

simultaneously. 

During PIPE# Operation: These signals are not used during 

PIPE# operation. 

During FRAME# Operation: These signal are not used during 

AGP FRAME# operation. 

Note: When sideband addressing is disabled, these signals are 

isolated (no external/internal pull-ups are required). 

NOTE: The above table contains two mechanisms, SBA and PIPE#, to queue requests by the AGP 

master. Note that the master can only use one mechanism. The master may not switch methods without 

a full reset of the system. When PIPE# is used to queue addresses, the master is not allowed to queue 

addresses using the SBA bus. For example, during configuration time, if the master indicates that it can 

use either mechanism, the configuration software will select which mechanism the master will use. 

Once this choice has been made, the master must continue to use the mechanism selected until the 

master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic 

mechanism, but rather a static decision when the device is first being configured after reset. 

AGP Status Signals 


ST[2:0] O Status: Provides information from the arbiter to an AGP Master on 

AGP what it may do. ST[2:0] only have meaning to the master when its 

GNT# is asserted. When GNT# is deasserted these signals have no 

meaning and must be ignored. 

During FRAME# Operation: These signals are not used during 

FRAME# based operation; except that a ‘111’ indicates that the 

master may begin a FRAME# transaction. 

AGP Flow Control Signals 


RBF# I 

AGP 

WBF# I 

AGP 

Read Buffer Full: Indicates if the master is ready to accept 

previously requested low priority read data. When RBF# is asserted, 

the MCH-M is not allowed to initiate the return of low priority read 

data. That is, the MCH-M can only finish returning the data for the 

request currently being serviced. RBF# is only sampled at the 

beginning of a cycle. 

If the AGP master is always ready to accept return read data then it 

is not required to implement this signal. 



Write-Buffer Full: indicates if the master is ready to accept Fast 

Write data from the MCH-M. When WBF# is asserted the MCH-M 

is not allowed to drive Fast Write data to the AGP master. WBF# is 

only sampled at the beginning of a cycle. 

If the AGP master is always ready to accept fast write data then it is 

not required to implement this signal. 



AGP Strobe Signals 


AD_STB0 I/O Address/Data Bus Strobe-0: provides timing for 2x and 4x data on 

(s/t/s) AD[15:0] and C/BE[1:0]# signals. The agent that is providing the 

AGP 

AD_STB0# I/O 

(s/t/s) 

AGP 

AD_STB1 I/O 

(s/t/s) 

AGP 

AD_STB1# I/O 

(s/t/s) 

AGP 

data will drive this signal. 

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SB_STB I 

AGP 

SB_STB# I 

AGP 

Address/Data Bus Strobe-0 Complement: With AD STB0, forms 

a differential strobe pair that provides timing information for the 

AD[15:0] and C/BE[1:0]# signals. The agent that is providing the 


Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on 

AD[31:16] and C/BE[3:2]# signals. The agent that is providing the 


Address/Data Bus Strobe-1 Complement: With AD STB1, forms 

a differential strobe pair that provides timing information for the 

AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is 

providing the data will drive this signal. 

Sideband Strobe: Provides timing for 2x and 4x data on the 

SBA[7:0] bus. The AGP master drives it after the system has been 

configured for 2x or 4x sideband address mode. 

Sideband Strobe Complement: The differential complement to the 

SB_STB signal. It is used to provide timing 4x mode. 

72



AGP/PCI Signals 


G_FRAME# I/O 

s/t/s 

AGP 

G_IRDY# I/O 

s/t/s 

AGP 

G_TRDY# I/O 

s/t/s 

AGP 

G_FRAME: Frame 

During PIPE# and SBA Operation: Not used by AGP SBA and 

PIPE# operations. 

During Fast Write Operation: Used to frame transactions as an 

output during Fast Writes. 

During FRAME# Operation: G_FRAME# is an output when the 

MCH-M acts as an initiator on the AGP Interface. G_FRAME# is 

asserted by the MCH-M to indicate the beginning and duration of an 

access. G_FRAME# is an input when the MCH-M acts as a 

FRAME#-based AGP target. As a FRAME#-based AGP target, the 

MCH-M latches the C/BE[3:0]# and the AD[31:0] signals on the 

first clock edge on which MCH-M samples FRAME# active. 

G_IRDY#: Initiator Ready 

During PIPE# and SBA Operation: Not used while enqueueing 

requests via AGP SBA and PIPE#, but used during the data phase of 

PIPE# and SBA transactions. 

During FRAME# Operation: G_IRDY# is an output when 

MCH-M acts as a FRAME#-based AGP initiator and an input when 

the MCH-M acts as a FRAME#-based AGP target. The assertion of 

G_IRDY# indicates the current FRAME#-based AGP bus initiator's 

ability to complete the current data phase of the transaction. 

During Fast Write Operation: In Fast Write mode, G_IRDY# 

indicates that the AGP-compliant master is ready to provide all 

write data for the current transaction. Once G_IRDY# is asserted for 

a write operation, the master is not allowed to insert wait states. The 

master is never allowed to insert a wait state during the initial data 

transfer (32 bytes) of a write transaction. However, it may insert 

wait states after each 32-byte block is transferred. 

G_TRDY#: Target Ready 

During PIPE# and SBA Operation: Not used while enqueueing 

requests via AGP SBA and PIPE#, but used during the data phase of 

PIPE# and SBA transactions. 

During FRAME# Operation: G_TRDY# is an input when the 

MCH-M acts as an AGP initiator and is an output when the 

MCH-M acts as a FRAME#-based AGP target. The assertion of 

G_TRDY# indicates the target’s ability to complete the current data 

phase of the transaction. 

During Fast Write Operation: In Fast Write mode, G_TRDY# 

indicates the AGP-compliant target is ready to receive write data for 

the entire transaction (when the transfer size is less than or equal to 

32 bytes) or is ready to transfer the initial or subsequent block (32 

bytes) of data when the transfer size is greater than 32 bytes. The 

target is allowed to insert wait states after each block (32 bytes) is 

transferred on write transactions. 


G_STOP# I/O 

s/t/s 

AGP 

G_STOP#: Stop 

During PIPE# and SBA Operation: This signal is not used during 

PIPE# or SBA operation. 

During FRAME# Operation: G_STOP# is an input when the 

MCH-M acts as a FRAME#-based AGP initiator and is an output 

when the MCH-M acts as a FRAME#-based AGP target. G_STOP# 

is used for disconnect, retry, and abort sequences on the AGP 

interface 

G_DEVSEL# G_ DEVSEL#: Device Select 

During PIPE# and SBA Operation: This signal is not used during 

PIPE# or SBA operation. 

During FRAME# Operation: G_DEVSEL#, when asserted, 

indicates that a FRAME#-based AGP target device has decoded its 

address as the target of the current access. The MCH-M asserts 

G_DEVSEL# based on the SDRAM address range being accessed 

by a PCI initiator. As an input, G_DEVSEL# indicates whether the 

G_REQ# I 

AGP 

G_GNT# O 

AGP 

G_AD[31:0] I/O 

AGP 

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G_PAR I/O 

AGP 

AGP master has recognized a PCI cycle to it. 

G_REQ#: Request 

During SBA Operation: This signal is not used during SBA 

operation. 

During PIPE# and FRAME# Operation: G_REQ#, when 

asserted, indicates that the AGP master is requesting use of the AGP 

interface to run a FRAME#- or PIPE#-based operation. 

G_GNT#: Grant 

During SBA, PIPE# and FRAME# Operation: G_GNT#, along 

with the information on the ST[2:0] signals (status bus), indicates 

how the AGP interface will be used next. 

G_AD[31:0]: Address/Data Bus 

During PIPE# and FRAME# Operation: The G_AD[31:0] 

signals are used to transfer both address and data information on the 

AGP interface. 

During SBA Operation: The G_AD[31:0] signals are used to 

transfer data on the AGP interface. 

G_PAR: Parity 

During FRAME# Operation: G_PAR is driven by the MCH-M 

when it acts as a FRAME#-based AGP initiator during address and 

data phases for a write cycle, and during the address phase for a 

read cycle. G_PAR is driven by the MCH-M when it acts as a 

FRAME#-based AGP target during each data phase of a 

FRAME#-based AGP memory read cycle. Even parity is generated 

across G_AD[31:0] and G_CBE[3:0]#. 

During SBA and PIPE# Operation: This signal is not used during 

SBA and PIPE# operation. 

73



AGP/PCI Signals (Continued) 


G_CBE[3:0]# I/O 

AGP 

G_CBE[3:0]#: Command/Byte Enable 

During FRAME# Operation: During the address phase of a 

transaction, the G_CBE[3:0]# signals define the bus command. 

During the data phase, the G_CBE[3:0]# signals are used as byte 

enables. The byte enables determine which byte lanes carry 

meaningful data. The commands issued on the G_CBE# signals 

during FRAME#-based AGP transactions are the same G_CBE# 

command described in the PCI 2.2 specification. 

During PIPE# Operation: When an address is enqueued using 

PIPE#, the C/BE# signals carry command information. The 

command encoding used during PIPE#-based AGP is different than 

the command encoding used during FRAME#-based AGP cycles 

(or standard PCI cycles on a PCI bus). 

During SBA Operation: These signals are not used during SBA 

operation. 

NOTE: PCIRST# from the ICH3-M is connected to RSTIN# and is used to reset AGP interface logic 

within the MCH-M. The AGP agent will also use PCIRST# provided by the ICH3-M as an input to 

reset its internal logic. 

Clocks, Reset and Miscellaneous Signals 


BCLK/BCLK# I Differential Host Clock In: These pins receive a differential host 

CMOS clock from the external clock synthesizer. This clock is used by all 

66IN I 

CMOS 

SCK[5:0] O 

CMOS 

SCK#[5:0] O 

CMOS 

RSTIN# I 

CMOS 

TESTIN# I 

CMOS 

of the MCH-M logic that is in the Host clock domain. 

66-MHz Clock In: This pin receives a 66-MHz clock from the 

clock synthesizer. This clock is used by AGP/PCI and hub interface 

clock domains. 

Note: That this clock input is 3.3-V tolerant. 

SDRAM Differential Clock (DDR): These signals deliver a source 

synchronous clock to the SO-DIMMs. There are three per 

SO-DIMM. 

SDRAM Inverted Differential Clock (DDR): These signals are 

the complement to the SCK[5:0] signals. There are three per 

SO-DIMM. 

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Reset In: When asserted this signal will asynchronously reset the 

MCH-M logic. This signal is connected to the PCIRST# output of 

the ICH3-M. All AGP/PCI output and bi-directional signals will 

also tri-state compliant to PCI Rev 2.0 and 2.1 specifications. 

Note: That this input needs to be 3.3-V tolerant. 

Test Input: This pin is used for manufacturing and board level test 

purposes. 

Note: This signal has an internal pullup resistor. 

Voltage Reference Signals 


HVREF Ref Host Reference Voltage. Reference voltage input for the Data, 

Address, and Common clock signals of the Host AGTL+ interface 

SDREF Ref DDR Reference Voltage: Reference voltage input for DQ, DQS, & 

RCVENIN#. 

HI_REF Ref Hub Interface Reference: Reference voltage input for the hub 

interface. 

AGPREF Ref AGP Reference: Reference voltage input for the AGP interface. 

HLRCOMP I/O Compensation for hub interface: This signal is used to calibrate 

CMOS the hub interface I/O buffers. 

GRCOMP I/O Compensation for AGP: This signal is used to calibrate AGP 

CMOS buffers. 

HRCOMP[1:0] I/O Compensation for Host: This signal is used to calibrate the Host 

CMOS AGTL+ I/O buffers. 

HSWNG[1:0] I Host Reference Voltage: Reference voltage input for the 

CMOS compensation logic. 

SMRCOMP I/O 

CMOS 

System Memory RCOMP 

VCC1_5 The 1.5 V Power input pins 

VCC1_8 The 1.8 V Power input pins 

VCCSM The SDRAM Power input pins. 2.5 V for DDR. 

VCCA[1:0] PLL power input pins. 

VTT The AGTL+ bus termination voltage inputs 

VSS GROUND 

VSSA[1:0] PLL Ground 

74


5.3 Intel 82801CAM I/O Controller Hub 3 (ICH3-M) 

Hub Interface Signals 


HI[11:0] I/O Hub Interface Signals 

HI_STB I/O Hub Interface Strobe: One of two differential strobe signals used 

to transmit and receive data through the hub interface. 

HI_STB# I/O Hub Interface Strobe Complement: Second of the two differential 

strobe signals. 

HICOMP I/O Hub Interface Compensation: Used for hub interface buffer 

compensation. 

HITERM I Hub Interface Termination: Analog input used to control the 

voltage swing and impedance strength of hub interface pins. The 

expected voltage is Vcc/2 for HI Normal Termination 

NOTE: Refer to the platform design guide for resistor values and 

routing guidelines. 

LAN Connect Interface Signals 


LAN_CLK I LAN I/F Clock: Driven by the LAN Connect component. 

Frequency range is 5 to 50 MHz. 

LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to 

transfer data and control information to the integrated LAN 

Controller. These signals have integrated weak pull-up resistors. 

LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals 

to transfer data and control information to the LAN Connect 

component. 

LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync 

signals are multiplexed onto this pin. 

EEPROM Interface Signals 


EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM. 

EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the ICH3. 

This signal has an integrated pull-up resistor. 

EE_DOUT O EEPROM Data Out: Transfers data from the ICH3 to the 

EEPROM. 

EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM. 

Firmware Hub Interface Signals 


FWH[3:0]/ 

I/O Firmware Hub Signals. Muxed with LPC address signals. 

LAD[3:0] 

FWH[4]/ 

LFRAME# 

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I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME# 

signal. 

PCI Interface Signals 


AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data 

bus. During the first clock of a transaction, AD[31:0] contain a 

physical address (32 bits). During subsequent clocks, AD[31:0] 

contain data. The ICH3 will drive all 0s on AD[31:0] during the 

address phase of all PCI Special Cycles. 

C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable 

signals are multiplexed on the same PCI pins. During the address 

phase of a transaction, C/BE[3:0]# define the bus command. During 

the data phase C/BE[3:0]# define the Byte Enables. 

C/BE[3:0]# Command Type 

0 0 0 0 Interrupt Acknowledge 

0 0 0 1 Special Cycle 

0 0 1 0 I/O Read 

0 0 1 1 I/O Write 

0 1 1 0 Memory Read 

0 1 1 1 Memory Write 

1 0 1 0 Configuration Read 

1 0 1 1 Configuration Write 

1 1 0 0 Memory Read Multiple 

1 1 1 0 Memory Read Line 

1 1 1 1 Memory Write and Invalidate 

All command encodings not shown are reserved. The ICH3 does not 

decode reserved values, and therefore will not respond if a PCI 

master generates a cycle using one of the reserved values. 

DEVSEL# I/O Device Select: The ICH3 asserts DEVSEL# to claim a PCI 

transaction. As an output, the ICH3 asserts DEVSEL# when a PCI 

master peripheral attempts an access to an internal ICH3 address or 

an address destined for the hub interface (main memory or AGP). 

As an input, DEVSEL# indicates the response to an ICH3-initiated 

transaction on the PCI bus. DEVSEL# is tri-stated from the leading 

edge of PCIRST#. DEVSEL# remains tri-stated by the ICH3 until 

driven by a Target device. 

75



PCI Interface Signals (Continued) 


FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the 

beginning and duration of a PCI transaction. While the initiator 

asserts FRAME#, data transfers continue. When the initiator negates 

FRAME#, the transaction is in the final data phase. FRAME# is an 

input to the ICH3 when the ICH3 is the target, and FRAME# is an 

output from the ICH3 when the ICH3 is the Initiator. FRAME# 

remains tri- stated by the ICH3 until driven by an Initiator. 

IRDY# I/O Initiator Ready: IRDY# indicates the ICH3’s ability, as an 

Initiator, to complete the current data phase of the transaction. It is 

used in conjunction with TRDY#. A data phase is completed on any 

clock both IRDY# and TRDY# are sampled asserted. During a 

write, IRDY# indicates the ICH3 has valid data present on 

AD[31:0]. During a read, it indicates the ICH3 is prepared to latch 

data. IRDY# is an input to the ICH3 when the ICH3 is the Target 

and an output from the ICH3 when the ICH3 is an Initiator. IRDY# 

remains tri-stated by the ICH3 until driven by an Initiator. 

TRDY# I/O Target Ready: TRDY# indicates the ICH3’s ability as a Target to 

complete the current data phase of the transaction. TRDY# is used 

in conjunction with IRDY#. A data phase is completed when both 

TRDY# and IRDY# are sampled asserted. During a read, TRDY# 

indicates that the ICH3, as a Target, has placed valid data on 

AD[31:0]. During a write, TRDY# indicates the ICH3, as a Target 

is prepared to latch data. TRDY# is an input to the ICH3 when the 

ICH3 is the Initiator and an output from the ICH3 when the ICH3 is 

a Target. TRDY# is tri-stated from the leading edge of PCIRST#. 

TRDY# remains tri-stated by the ICH3 until driven by a target. 

STOP# I/O Stop: STOP# indicates that the ICH3, as a Target, is requesting the 

Initiator to stop the current transaction. STOP# causes the ICH3, as 

an Initiator, to stop the current transaction. STOP# is an output 

when the ICH3 is a Target and an input when the ICH3 is an 

Initiator. STOP# is tri-stated from the leading edge of 

PCIRST#. STOP# remains tri-stated until driven by the ICH3. 

PERR# I/O Parity Error: An external PCI device drives PERR# when it 

receives data that has a parity error. The ICH3 drives PERR# when 

it detects a parity error. The ICH3 can either generate an NMI# or 

SMI# upon detecting a parity error (either detected internally or 

reported via the PERR# signal). 

SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that 

detects a system error condition. Upon sampling SERR# active, the 

ICH3 has the ability to generate an NMI, SMI#, or interrupt. 

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PAR I/O Calculated/Checked Parity: PAR uses “even” parity calculated on 

36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the 

ICH3 counts the number of “1”s within the 36 bits plus PAR and the 

sum is always even. The ICH3 always calculates PAR on 36 bits 

regardless of the valid byte enables. The ICH3 generates PAR for 

address and data phases and only guarantees PAR to be valid one 

PCI clock after the corresponding address or data phase. The ICH3 

drives and tri-states PAR identically to the AD[31:0] lines except 

that the ICH3 delays PAR by exactly one PCI clock. PAR is an 

output during the address phase (delayed one clock) for all ICH3 

initiated transactions. PAR is an output during the data phase 

(delayed one clock) when the ICH3 is the Initiator of a PCI write 

transaction, and when it is the Target of a read transaction. ICH3 

checks parity when it is the Target of a PCI write transaction. If a 

parity error is detected, the ICH3 will set the appropriate internal 

status bits, and has the option to generate an NMI# or SMI#. 

REQ[4:0]# 

I PCI Requests: Supports up to 6 masters on the PCI bus. REQ[5]# 

REQ[5]#/ 

is muxed with PC/PCI REQ[B]# (must choose one or the other, but 

REQ[B]#/ 

GPIO[1] 

not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can 

instead be used as GPIO[1]. 

NOTE: REQ[0]# is programmable to have improved arbitration 

latency for supporting PCI-based 1394 controllers. 

GNT[4:0]# 

O PCI Grants: Supports up to 6 masters on the PCI bus. GNT[5]# is 

GNT[5]#/ 

muxed with PC/PCI GNT[B]# (must choose one or the other, but 

GNT[B]#/ 

not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be 

GPIO[17] 

used as a GPIO. 

Pull-up resistors are not required on these signals. If pull-ups are 

used, they should be tied to the Vcc3_3 power rail. 

GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. 

PCICLK I PCI Clock: 33 MHz clock. PCICLK provides timing for all 

transactions on the PCI Bus. 

NOTE: This clock does not stop based on STP_PCI# signal. PCI 

Clock only stops based on SLP_S1# or SLP_S3#. 

PCIRST# O PCI Reset: ICH3 asserts PCIRST# to reset devices that reside on 

the PCI bus. The ICH3 asserts PCIRST# during power-up and when 

S/W initiates a hard reset sequence through the RC (CF9h) register. 

The ICH3 drives PCIRST# inactive a minimum of 1 ms after 

PWROK is driven active. The ICH3 drives PCIRST# active a 

minimum of 1 ms when initiated through the RC register. 

PLOCK# I/O PCI Lock: Indicates an exclusive bus operation and may require 

multiple transactions to complete. ICH3 asserts PLOCK# when it 

performs non-exclusive transactions on the PCI bus. Devices on the 

PCI bus (other than the ICH3) are not permitted to assert the 

PLOCK# signal. 

76



PCI Interface Signals (Continued) 


PME# I/OD PCI Power Management Event: PCI peripherals drive PME# to 

wake the system from low-power states S1-S5. PME# assertion can 

also be enabled to generate an SCI from the S0 state. In some cases 

the ICH3 may drive PME# active due to an internal wake event. The 

ICH3 will not drive PME# high, but it will be pulled up to 

CLKRUN#. 

GPIO[24] 

REQ[A]#/ 

GPIO[0] 

REQ[B]#/ 

REQ[5]#/ 

GPIO[1] 

GNT[A]#/ 

GPIO[16] 

GNT[B]#/ 

GNT[5]#/ 

GPIO[17] 

VccSus3_3 by an internal pull-up resistor. 

I/O PCI Clock Run: Used to support PCI Clock Run protocol. 

Connects to PCI devices that need to request clock re-start, or 

prevention of clock stopping. 

NOTE: An external pull-up to the core power plane is required. 

I PC/PCI DMA Request [B:A]: This request serializes ISA-like 

DMA Requests for the purpose of running ISA-compatible DMA 

cycles over the PCI bus. This is used by devices such as PCI based 

Super I/O or audio codecs which need to perform legacy Intel ® 

8237 DMA but have no ISA bus. 

When not used for PC/PCI requests, these signals can be used as 

General Purpose Inputs. REQ[B]# can instead be used as the sixth 

PCI bus request. 

O PC/PCI DMA Acknowledges [B: A]: This grant serializes an 

ISA-like DACK# for the purpose of running DMA/ISA Master 

cycles over the PCI bus. This is used by devices such as PCI based 

Super/IO or audio codecs which need to perform legacy Intel 8237 

DMA but have no ISA bus. 

When not used for PC/PCI, these signals can be used as General 

Purpose Outputs. GNTB# can also be used as the sixth PCI bus 

master grant output. 

These signal have internal pull-up resistors. 

IDE Interface Signals 


PDCS1#, SDCS1# O Primary and Secondary IDE Device Chip Selects for 100 Range: 

For ATA command register block. This output signal is connected 

to the corresponding signal on the primary or secondary IDE 

connector. 

PDCS3#, SDCS3# O Primary and Secondary IDE Device Chip Select for 300 Range: 

For ATA control register block. This output signal is connected to 

the corresponding signal on the primary or secondary IDE 

PDA[2:0], 

SDA[2:0] 

connector. 

O Primary and Secondary IDE Device Address: These output 

signals are connected to the corresponding signals on the primary or 

secondary IDE connectors. They are used to indicate which byte in 

either the ATA command block or control block is being addressed. 


PDD[15:0], 

SDD[15:0] 

PDDREQ, 

SDDREQ 

PDDACK#, 

SDDACK# 

PDIOR#/ 

(PDWSTB/PRDMA 

RDY#) 

SDIOR#/ 

(SDWSTB/SRDMA 

RDY#) 

I/O Primary and Secondary IDE Device Data: These signals directly 

drive the corresponding signals on the primary or secondary IDE 

connector. There is a weak internal pull-down resistor on PDD[7] 

and SDD[7]. 

I Primary and Secondary IDE Device DMA Request: These input 

signals are directly driven from the DRQ signals on the primary or 

secondary IDE connector. It is asserted by the IDE device to request 

a data transfer, and used in conjunction with the PCI bus master IDE 

function and are not associated with any AT compatible DMA 

channel. There is a weak internal pull-down resistor on these 

signals. 

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PDIOW#/ 

(PDSTOP) 

SDIOW#/ 

(SDSTOP) 

O Primary and Secondary IDE Device DMA Acknowledge: These 

signals directly drive the DAK# signals on the primary and 

secondary IDE connectors. Each is asserted by the ICH3 to indicate 

to IDE DMA slave devices that a given data transfer cycle (assertion 

of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is 

used in conjunction with the PCI bus master IDE function and are 

not associated with any AT-compatible DMA channel. 

O Primary and Secondary Disk I/O Read (PIO and Non-Ultra 

DMA): This is the command to the IDE device that it may drive 

data onto the PDD or SDD lines. Data is latched by the ICH3 on the 

deassertion edge of PDIOR# or SDIOR#. The IDE device is 

selected either by the ATA register file chip selects (PDCS1# 

or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the 

IDE DMA acknowledge (PDDAK# or SDDAK#). 

Primary and Secondary Disk Write Strobe (Ultra DMA Writes 

to Disk): This is the data write strobe for writes to disk. When 

writing to disk, ICH3 drives valid data on rising and falling edges of 

PDWSTB or SDWSTB. 

Primary and Secondary Disk DMA Ready (Ultra DMA Reads 

from Disk): This is the DMA ready for reads from disk. When 

reading from disk, ICH3 deasserts PRDMARDY# or 

SRDMARDY# to pause burst data transfers. 

O Primary and Secondary Disk I/O Write (PIO and Non-Ultra 

DMA): This is the command to the IDE device that it may latch 

data from the PDD or SDD lines. Data is latched by the IDE device 

on the deassertion edge of PDIOW# or SDIOW#. The IDE device is 

selected either by the ATA register file chip selects (PDCS1# or 

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the 

IDE DMA acknowledge (PDDAK# or SDDAK#). 

Primary and Secondary Disk Stop (Ultra DMA): ICH3 asserts 

this signal to terminate a burst. 

77



IDE Interface Signals (Continued) 


PIORDY#/ 

(PDRSTB/PWDMA 

RDY#) 

SIORDY#/ 

(SDRSTB/SWDMA 

RDY#) 

I Primary and Secondary I/O Channel Ready (PIO): This signal 

will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# 

or SDIOW# on writes) longer than the minimum width. It adds wait 

states to PIO transfers. 

Primary and Secondary Disk Read Strobe (Ultra DMA Reads 

from Disk): When reading from disk, ICH3 latches data on rising 

and falling edges of this signal from the disk. 

Primary and Secondary Disk DMA Ready (Ultra DMA Writes 

to Disk): When writing to disk, this is de-asserted by the disk to 

pause burst data transfers. 

Interrupt Signals 


SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt 

protocol. 

PIRQ[D”A]# I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals 

can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as 

described in the Interrupt Steering section. Each PIRQx# line has a 

separate Route Control Register. 

In APIC mode, these signals are connected to the internal I/O APIC 

in the following fashion: PIRQ[A]# is connected to IRQ16, 

PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. 

PIRQ[H:E]#/ 

GPIO[5:2] 

This frees the legacy interrupts. 

I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals 

can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as 

described in the Interrupt Steering section. Each PIRQx# line has a 

separate Route Control Register. 

In APIC mode, these signals are connected to the internal I/O APIC 

in the following fashion: PIRQ[E]# is connected to IRQ20, 

PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. 

This frees the legacy interrupts. If not needed for interrupts, these 

IRQ[15:14] I 

signals can be used as GPIO. 

Interrupt Request 15–14: These interrupt inputs are connected to 

the IDE drives. IRQ14 is used by the drives connected to the 

Primary controller and IRQ15 is used by the drives connected to the 

Secondary controller. 

APICCLK I APIC Clock: This clock operates up to 33.33 MHz. 

APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to 

send and receive data over the APIC bus. As inputs the data is valid 

on the rising edge of APICCLK. As outputs, new data is driven 

from the rising edge of the APICCLK. 

LPC Interface Signals 


LAD[3:0]/ 

I/O LPC Multiplexed Command, Address, Data: Internal pull-ups are 

FWH[3:0] 

provided. 

LFRAME#/ 

O LPC Frame: Indicates the start of an LPC cycle, or an abort. 

FWH[4] 

LDRQ[1:0]# I LPC Serial DMA/Master Request Inputs: Used to request DMA 

or bus master access. Typically connected to external Super I/O 

device. An internal pull-up resistor is provided on these signals. 

USB Interface Signals 


USBP0P, 

I/O Universal Serial Bus Port 1:0 Differential: These differential 

USBP0N, 

pairs are used to transmit Data/Address/Command signals for ports 

USBP1P, 

0 and 1. These ports are routed to USB 1.1 Controller #1. 

USBP1N 

NOTE: No external resistors are required on these signals. The 

ICH3 integrates 15 k pull-downs and provides an output driver 

USBP2P, 

USBP2N, 

USBP3P, 

USBP3N 

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impedance of 45 . which requires no external series resistor. 





ICH3 integrates 15 k pull-downs and provides an output driver 

impedance of 45 . which requires no external series resistor. 

USBP4P, 


USBP4N, 


USBP5P, 


USBP4N 


ICH3 integrates 15 k pull-downs and provides an effective output 

driver impedance of 45 . that requires no external series resistor. 

OC[5:0]# I/O Overcurrent Indicators: These signals set corresponding bits in 

the USB controllers to indicate that an overcurrent condition has 

occurred. 

USBRBIAS I USB Resistor Bias: Analog connection for an external 18.2 . 

resistor (± 1%) to ground, used to set transmit current and internal 

load resistors. 

78



Power Management Interface Signals 


THRM# I Thermal Alarm: Active low signal generated by external hardware 

to start the Hardware clock throttling mode. Can also generate an 

SMI# or an SCI. 

SLP_S1# O S1 Sleep Control: Clock Synthesizer or Power plane control. 

Connects to Clock Synthesizer’s PWRDWN# signal. Optional use is 

to shut off power to non-critical systems when in the S1 (Powered 

On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk) or S5 

(Soft Off) states. 

SLP_S3# O S3 Sleep Control: Power plane control. Shuts off power to all 

non-critical systems when in S3 (Suspend To RAM), S4 (Suspend 

to Disk) or S5 (Soft Off) states. 

SLP_S5# O S5 Sleep Control: Power plane control. The signal is used to shut 

power off to all non-critical systems when in the S4 (Suspend To 

Disk) or S5 (Soft Off) states. 

PWROK I Power OK: When asserted, PWROK is an indication to the ICH3 

that core power and PCICLK have been stable for at least 1 ms. 

PWROK can be driven asynchronously. When PWROK is negated, 

the ICH3 asserts PCIRST#. 

NOTE: PWROK must deassert for a minimum of 3 RTC clock 

periods in order for the ICH3 to fully reset the power and properly 

generate the PCIRST# output 

PWRBTN# I Power Button: The Power Button will cause SMI# or SCI to 

indicate a system request to go to a sleep state. If the system is 

already in a sleep state, this signal will cause a wake event. If 

RI# I 

PWRBTN# is pressed for more than 4 seconds, this will cause an 

unconditional transition (power button override) to the S5 state with 

only the PWRBTN# available as a wake event. Override will occur 

even if the system is in the S1-S4 states. This signal has an internal 

pull-up resistor. 

Ring Indicate: From the modem interface. Can be enabled as a 

wake event, and this is preserved across power failures. 

RSMRST# I Resume Well Reset: Used for resetting the resume power plane 

logic. 

LAN_RST# I LAN Reset: This signal must be asserted at least 10 ms after the 

SUS_STAT#/ 

LPCPD# 

resume well power (VccLAN3_3 and VccLAN1_8) is valid. When 

deasserted, this signal is an indication that the resume well power is 

stable. 

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O Suspend Status: This signal is asserted by the ICH3 to indicate that 

the system will be entering a low power state soon. This can be 

monitored by devices with memory that need to switch from normal 

refresh to suspend refresh mode. It can also be used by other 

peripherals as an indication that they should isolate their outputs 

that may be going to powered-off planes. This signal is called 

LPCPD# on the LPC I/F. 


C3_STAT# O C3_STAT#: This signal will typically be configured as C3_STAT#. 

It is used for indicating to an AGP device that a C3 state transition 

is beginning or ending. If C3_STAT# functionality is not required, 

this signal may be used as a GPO. 

NOTE: This signal will be asserted in S1-D and S1-M on ICH3-M. 

SUSCLK O Suspend Clock: Output of the RTC generator circuit to use by other 

chips for refresh clock. 

AGPBUSY# I AGP Bus Busy: To support the C3 state. Indication that the AGP 

device is busy. When this signal is asserted, the BM_STS bit will be 

set. If this functionality is not needed, this signal may be configured 

as a GPI. 

STP_PCI# O Stop PCI Clock: This signal is an output to the external clock 

generator for it to turn off the PCI clock. Used to support PCI 

CLKRUN# protocol. If this functionality is not needed, this signal 

can be configured as a GPO. 

STP_CPU# O Stop CPU Clock: Output to the external clock generator for it to 

turn off the processor clock. Used to support the C3 state. If this 

functionality is not needed, this signal can be configured as a GPO. 

BATLOW# I Battery Low: Input from battery to indicate that there is insufficient 

power to boot the system. Assertion will prevent wake from S1-S5 

state. Can also be enabled to cause an SMI# when asserted. 

CPUPERF# OD CPU Performance: Used for Intel ® SpeedStep technology 

support. Selects which power state to put the processor in. This is an 

open-drain output signal, and requires an external pull-up to the 

processor I/O voltage. 

SSMUXSEL O SpeedStep Mux Select: Used for Intel SpeedStep technology 

support. Selects the voltage level for the processor. 

VGATE I VRM Power Good Gate: Used for Intel SpeedStep technology 

support. This is an output from the processor’s voltage regulator to 

indicate that the voltage is stable. May go inactive during an Intel 

SpeedStep transition. In non-Intel SpeedStep technology systems 

this signal should be connected to the processor VRM Power Good. 

DPRSLPVR O Deeper Sleep—Voltage Regulator: Used to lower the voltage of 

VRM during C4 and S1-M states. When the signal is high, the 

voltage regulator outputs the lower “Deeper Sleep” voltage. When 

the signal is low (default) the voltage regulator outputs the higher 

“Normal” voltage. During PCIRST#, the output driver is disabled 

and an internal pull-down is enabled. This is needed for 

implementing a strap on the pin. When PCIRST# deasserts, the 

output driver is enabled. In order to guarantee no glitches on the 

DPRSLPVR pin, the pull-down is disabled after the output driver is 

fully enabled. 

NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a 

functional strap. 

79



Processor Interface Signals 


A20M# O Mask A20: A20M# will go active based on either setting the 

appropriate bit in the Port 92h register, or based on the A20GATE 

input being active. 

Speed Strap: During the reset sequence, ICH3 drives A20M# high 

if the corresponding bit is set in the FREQ_STRP register. 

CPUSLP# O CPU Sleep: This signal puts the processor into a state that saves 

substantial power compared to Stop-Grant state. However, during 

that time, no snoops occur. The ICH3 can optionally assert the 

CPUSLP# signal when going to the S1 state. 

FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor 

error signal on the processor. FERR# is only used if the ICH3 

coprocessor error reporting function is enabled in the General 

Control Register (Device 31:Function 0, Offset D0, bit 13). If 

FERR# is asserted, the ICH3 generates an internal IRQ13 to its 

interrupt controller unit. It is also used to gate the IGNNE# signal to 

ensure that IGNNE# is not asserted to the processor unless FERR# 

is active. FERR# requires an external weak pull-up to ensure a high 

level when the coprocessor error function is disabled. 

NOTE: FERR# can be used in some states for notification by the 

processor of pending interrupt events (this functionality is 

independent of the General Control Register bit setting). 

IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error 

pin on the processor. IGNNE# is only used if the ICH3 coprocessor 

error reporting function is enabled in the General Control Register 

(Device 31:Function 0, Offset D0, bit 13). If FERR# is active, 

indicating a coprocessor error, a write to the Coprocessor Error 

Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains 

asserted until FERR# is negated. If FERR# is not asserted when the 

Coprocessor Error Register is written, the IGNNE# signal is not 

asserted. 

Speed Strap: During the reset sequence, ICH3 drives IGNNE# high 

if the corresponding bit is set in the FREQ_STRP register. 

INIT# O Initialization: INIT# is asserted by the ICH3 for 16 PCI clocks to 

reset the processor. ICH3 can be configured to support CPU BIST. 

In that case, INIT# will be active when PCIRST# is active. 

INTR O Processor Interrupt: INTR is asserted by the ICH3 to signal the 

processor that an interrupt request is pending and needs to be 

serviced. It is an asynchronous output and normally driven low. 

Speed Strap: During the reset sequence, ICH3 drives INTR high if 

the corresponding bit is set in the FREQ_STRP register. 

A20GATE I A20 Gate: From the keyboard controller. Acts as an alternative 

method to force the A20M# signal active. Saves the external OR 

gate needed with various other PCIsets. 

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NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable 

interrupt to the processor. The ICH3 can generate an NMI when 

either SERR# or IOCHK# is asserted. The processor detects an NMI 

when it detects a rising edge on NMI. NMI is reset by setting the 

corresponding NMI source enable/disable bit in the NMI Status and 

Control Register. 

Speed Strap: During the reset sequence, ICH3 drives NMI high if 

the corresponding bit is set in the FREQ_STRP register. 

SMI# O System Management Interrupt: SMI# is an active low output 

synchronous to PCICLK. It is asserted by the ICH3 in response to 

one of many enabled hardware or software events. 

STPCLK# O Stop Clock Request: STPCLK# is an active low output 

synchronous to PCICLK. It is asserted by the ICH3 in response to 

one of many hardware or software events. When the processor 

samples STPCLK# asserted, it responds by stopping its internal 

clock. 

RCIN# I Keyboard Controller Reset CPU: The keyboard controller can 

generate INIT# to the processor. This saves the external OR gate 

with the ICH3’s other sources of INIT#. When the ICH3 detects the 

assertion of this signal, INIT# is generated for 16 PCI clocks. 

Note that the ICH3 will ignore RCIN# assertion during transitions 

to the S1, S3, S4 and S5 states. 

CPUPWRGD OD CPU Power Good: Should be connected to the processor’s 

PWRGOOD input. To allow for Intel ® SpeedStep technology 

support, this signal is kept high during a Intel SpeedStep technology 

state transition to prevent loss of processor context. This is an 

open-drain output signal (external pull-up resistor required) that 

represents a logical AND of the ICH3’s PWROK and VGATE / 

VRMPWRGD signals. 

DPSLP# O Deeper Sleep: Asserted by the ICH3 to the processor. When the 

signal is low, the processor enters the Deep Sleep state by gating off 

the processor Core clock inside the processor. When the signal is 

high (default), the processor is not in the Deep Sleep state. This 

signal behaves identically to the STP_CPU# signal, but at the 

processor voltage level. 

80



SMBus Interface Signals 


SMBDATA I/OD SMBus Data: External pull-up is required. 

SMBCLK I/OD SMBus Clock: External pull-up is required. 

SMBALERT#/ 

GPIO[11] 

I SMBus Alert: This signal is used to wake the system or generate 

SMI#. If not used for SMBALERT#, it can be used as a GPI. 

System Management Interface Signals 


INTRUDER# I Intruder Detect: Can be set to disable system if box detected open. 

This signal’s status is readable, so it can be used like a GPI if the 

Intruder Detection is not needed. 

SMLINK[1:0] I/OD System Management Link: SMBus link to optional external 

system management ASIC or LAN controller. External pull-ups are 

required. 

Note that SMLINK[0] corresponds to an SMBus Clock signal, and 

SMLINK[1] corresponds to an SMBus Data signal. 

Real Time Clock Interface Signals 


RTCX1 Special Crystal Input 1: Connected to the 32.768 kHz crystal. If no 

external crystal is used, then RTCX1 can be driven with the desired 

clock rate. 

RTCX2 Special Crystal Input 2: Connected to the 32.768 kHz crystal. If no 

external crystal is used, then RTCX2 should be left floating. 

Other Clock Signals 


CLK14 I Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. 

This clock is permitted to stop during S1 (or lower) states. 

CLK48 I 48 MHz Clock: Used to run the USB controller. Runs at 48 MHz. 


CLK66 I 66 MHz Clock: Used to run the hub interface. Runs at 66 MHz. 


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Miscellaneous Signals 


SPKR O Speaker: The SPKR signal is the output of counter 2 and is 

internally “ANDed” with Port 61h bit 1 to provide Speaker Data 

Enable. This signal drives an external speaker driver device, which 

in turn drives the system speaker. Upon PCIRST#, its output state is 

0. 

NOTE: SPKR is sampled at the rising edge of PWROK as a 

functional strap. There is a weak integrated pull-down resistor on 

SPKR pin. 

RTCRST# I RTC Reset: When asserted, this signal resets register bits in the 

RTC well and sets the RTC_PWR_STS bit (bit 2 in 

GEN_PMCON3 register). 

NOTES: 

1. Clearing CMOS in an ICH3-based platform can be done by using 

a jumper on RTCRST# or GPI, or using SAFEMODE strap. 

Implementations should not attempt to clear CMOS by using a 

jumper to pull VccRTC low. Unless entering the XOR Chain Test 

Mode, the RTCRST# input must always be high when all other 

RTC power planes are on 

AC’97 Link Signals 


AC_RST# O AC ’97 Reset: Master H/W reset to external Codec(s) 

AC_SYNC O AC ’97 Sync: 48 kHz fixed rate sample sync to the Codec(s) 

AC_BIT_CLK I AC ’97 Bit Clock: 12.288 MHz serial data clock generated by the 

external Codec(s). This signal has an integrated pull-down resistor 

(see following note). 

AC_SDOUT O AC ’97 Serial Data Out: Serial TDM data output to the Codec(s) 

NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a 

functional strap. 

AC_SDIN[1:0] I AC ’97 Serial Data In 0: Serial TDM data inputs from the Codecs. 

81



General Purpose I/O Signals 


GPIO[47:44] I/O Not implemented. 

GPIO[43:38] I/O Can be input or output. Main power well. 

GPIO[37:32] I/O Can be input or output. Main power well. 

GPIO[31:29] O Not implemented. 

GPIO[28:27] I/O Can be input or output. Resume power well. Unmuxed. 

GPIO[26] I/O Not implemented. 

GPIO[25] I/O Can be input or output. Resume power well. Unmuxed. 

GPIO[24] I/O Not implemented. 

GPIO[23] O Not implemented. 

GPIO[22] OD Not implemented. 

GPIO[21] O Fixed as output only. Main power well. Can be used instead as 

C3_STAT#. 




GPIO[17:16] O Fixed as Output only. Main Power Well. Can be used instead as 

PC/PCI GNT[B:A]#. GPIO[17] can also alternatively be used for 

PCI GNT[5]#. Integrated pull-up resistor. 

GPIO[15:14] I Not implemented. 

GPIO[13:12] I Fixed as Input only. Resume Power Well. Unmuxed. 

GPIO[11] I Fixed as Input only. Resume Power Well. Can be used instead as 

SMBALERT#. 

GPIO[10:9] I Not implemented. 

GPIO[8] I Fixed as Input only. Resume Power Well. Unmuxed. 

GPIO[7] I Fixed as Input only. Main power well. Unmuxed. 

GPIO[6] I Fixed as Input only. Main power well. This GPIO is not 

implemented and is used instead as AGPBUSY#. 

GPIO[5:2] I Fixed as Input only. Main power well. Can be used instead as 

PIRQ[H:E]#. 

GPIO[1:0] I Fixed as Input only. Main Power Well. Can be used instead as 

PC/PCI REQ[B:A]#. GPIO[1] can also alternatively be used for PCI 

REQ[5]#. 

NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO are 

not 5V tolerant. 

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Power and Ground Signals 


VCC3_3[14:0] 3.3 V supply for Core well I/O buffers. This power may be shut off 

in S3, S5 or G3 states. 

VCC1_8[11:0] 1.8 V supply for Core well logic. This power may be shut off in S3, 

S5 or G3 states. 

V5REF[2:1] Reference for 5V tolerance on Core well inputs. This power may be 

shut off in S3, S5 or G3 states. 

HIREF 0.9 V reference for the hub interface. 

This power is shut off in S3, S5 or G3 states. 

VCCSUS3_3[5:0] 3.3 V supply for Resume well I/O buffers. This power is not 

expected to be shut off unless the main battery is removed or 

completely drained and AC power is not available. 

VCCSUS1_8[9:0] 1.8 V supply for Resume well logic. This power is not expected to 

be shut off unless the main battery is removed or completely drained 

and AC power is not available. 

V5REF_SUS[2:1] Reference for 5 V tolerance on Resume well inputs. This power is 

not expected to be shut off unless the main battery is removed or 

completely drained and AC power is not available. 

VCCLAN3_3[1:0] 3.3 V supply for LAN Connect interface buffers. This is a separate 

power plane that may or may not be energized in S3 -S5 states 

depending upon the presence or absence of AC power and network 

connectivity. This plane must be on in S0 and S1. 

VCCLAN1_8[2:0] 1.8 V supply for LAN controller logic. This is a separate power 

plane that may or may not be energized in S3 -S5 states depending 

upon the presence or absence of AC power and network 

connectivity. This plane must be on in S0 and S1. 

VCCRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. 

This power is not expected to be shut off unless the RTC battery is 

removed or completely drained. 

NOTE: Implementations should not attempt to clear CMOS by 

using a jumper to pull VccRTC low. Clearing CMOS in an 

ICH3-based platform can be done by using a jumper on RTCRST# 

or GPI, or using SAFEMODE strap. 

VBIAS RTC well bias voltage. The DC reference voltage applied to this pin 

sets a current that is mirrored throughout the oscillator and buffer 

circuitry. 

V_CPU_IO[2:0] Powered by the same supply as the processor I/O voltage. This 

supply is used to drive the processor I/F outputs. 

VSS[103:0] Grounds. 

82


5.4 RTL8139C(L) Ethernet Controller 

Power Management/Isolation Interface 

Signal Name Pin# Type Function 

PMEB 

(PME#) 

ISOLATEB 

(ISOLATE#) 

LWAKE/ 

CSTSCHG 

AD31-0 120-123, 

125-128, 4-6, 

8-11, 13, 

26-29, 31-34, 

37-39, 41-45 

76 O/D Power Management Event: Open drain, active low. Used 

by the RTL8139C(L) to request a change in its current 

power management state and/or to indicate that a power 

management event has occurred. 

95 I Isolate Pin: Active low. Used to isolate the RTL8139C(L) 

from the PCI bus. The RTL8139C(L) does not drive its PCI 

outputs (excluding PME#) and does not sample its PCI 

input (including RST# and PCICLK) as long as the Isolate 

pin is asserted. 

83 O LAN WAKE-UP Signal (When CardB_En=0, bit2 

Config3): This signal is used to inform the motherboard to 

execute the wake-up process. The motherboard must 

support Wake-On-LAN (WOL). There are 4 choices of 

output, including active high, active low, positive pulse, 

and negative pulse, that may be asserted from the LWAKE 

pin. Please refer to the LWACT bit in the CONFIG1 

register and the LWPTN bit in the CONFIG4 register for 

the setting of this output signal. The default output is an 

active high signal. 

Once a PME event is received, the LWAKE and PMEB 

assert at the same time when the LWPME (bit4, CONFIG4) 

is set to 0. If the LWPME is set to 1, the LWAKE asserts 

only when the PMEB asserts and the ISOLATEB is low. 

CSTSCHG Signal (When CardB_En=1, bit2 Config3): 

This signal is used in CardBus applications only and is used 

to inform the motherboard to execute the wake-up process 

whenever a PME event occurs. This is always an active 

high signal, and the setting of LWACT (bit 4, Config1), 

LWPTN (bit2, Config4), and LWPME (bit4, Config4) 

mean nothing in this case. 

This pin is a 3.3V signaling output pin. 

T/S PCI address and data multiplexed pins. 

C/BE3-0 2,14,24,36 T/S PCI bus command and byte enables multiplexed pins. 

CLK 116 I Clock: This PCI Bus clock provides timing for all 

transactions and bus phases, and is input to PCI devices. 

The rising edge defines the start of each phase. The clock 

frequency ranges from 0 to 33MHz. 

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Power Management/Isolation Interface Continued 


CLKRUNB 75 I/O Clock Run: This signal is used by the RTL8139C(L) to 

request starting (or speeding up) the clock, CLK. 

CLKRUNB also indicates the clock status. For the 

RTL8139C(L), CLKRUNB is an open drain output as well 

as an input. The RTL8139C(L) requests the central 

resource to start, speed up, or maintain the interface clock 

by the assertion of CLKRUNB. For the host system, it is an 

S/T/S signal. The host system (central resource) is 

responsible for maintaining CLKRUNB asserted, and for 

driving it high to the negated (deasserted) state. 

DEVSELB 19 S/T/S Device Select: As a bus master, the RTL8139C(L) samples 

this signal to insure that a PCI target recognizes the 

destination address for the data transfer. As a target, the 

RTL8139C(L) asserts this signal low when it recognizes its 

target address after FRAMEB is asserted. 

FRAMEB 15 S/T/S Cycle Frame: As a bus master, this pin indicates the 

beginning and duration of an access. FRAMEB is asserted 

low to indicate the start of a bus transaction. While 

FRAMEB is asserted, data transfer continues. 

When FRAMEB is deasserted, the transaction is in the final 

data phase. 

As a target, the device monitors this signal before decoding 

the address to check if the current transaction is addressed 

to it. 

GNTB 117 I Grant: This signal is asserted low to indicate to the 

RTL8139C(L) that the central arbiter has granted 

ownership of the bus to the RTL8139C(L). This input is 

used when the RTL8139C(L) is acting as a bus master. 

REQB 118 T/S Request: The RTL8139C(L) will assert this signal low to 

request the ownership of the bus from the central arbiter. 

IDSEL 3 I Initialization Device Select: This pin allows the 

RTL8139C(L) to identify when configuration read/write 

transactions are intended for it. 

INTAB 114 O/D Interrupt A: Used to request an interrupt. It is asserted low 

when an interrupt condition occurs, as defined by the 

Interrupt Status, Interrupt Mask and Interrupt Enable 

registers. 

83



Power Management/Isolation Interface Continued 


IRDYB 16 S/T/S Initiator Ready: This indicates the initiating agent’s ability 

to complete the current data phase of the transaction. 

As a bus master, this signal will be asserted low when the 

RTL8139C(L) is ready to complete the current data phase 

transaction. 

This signal is used in conjunction with the TRDYB signal. 

Data transaction takes place at the rising edge of CLK 

when both IRDYB and TRDYB are asserted low. As a 

target, this signal indicates that the master has put data on 

the bus. 

TRDYB 17 S/T/S Target Ready: This indicates the target agent’s ability to 

complete the current phase of the transaction. 

As a bus master, this signal indicates that the target is ready 

for the data during write operations and with the data 

during read operations. As a target, this signal will be 

asserted low when the (slave) device is ready to complete 

the current data phase transaction. This signal is used in 

conjunction with the IRDYB signal. Data transaction takes 

place at the rising edge of CLK when both IRDYB and 

TRDYB are asserted low. 

PAR 23 T/S Parity: This signal indicates even parity across AD31-0 

and C/BE3-0 including the PAR pin. As a master, PAR is 

asserted during address and write data phases. As a target, 

PERRB 21 

PAR is asserted during read data phases. 

S/T/S Parity Error: When the RTL8139C(L) is the bus master 

and a parity error is detected, the RTL8139C(L) asserts 

both SERR bit in ISR and Configuration Space command 

bit 8. Next, it completes the current data burst transaction, 

then stops operation and resets itself. After the host clears 

the system error, the RTL8139C(L) continues its operation. 

When the RTL8139C(L) is the bus target and a parity error 

is detected, the RTL8139C(L) asserts this PERRB pin low. 

SERRB 22 O/D System Error: If an address parity error is detected and 

Configuration Space Status register bit 15 (detected parity 

error) is enabled, RTL8139C(L) asserts both SERRB pin 

low and bit 14 of Status register in Configuration Space. 

STOP 20 S/T/S Stop: Indicates the current target is requesting the master to 

stop the current transaction. 

RSTB 115 I Reset: When RSTB is asserted low, the RTL8139C(L) 

performs an internal system hardware reset. RSTB must be 

held for a minimum of 120 ns. 

FLASH/EEPROM Interface 


MA16-3 

MA8 

70-63,61 

60,57, 

53-51 

61 

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O 

I/O 

Boot PROM Address Bus: These pins are used to access 

up to a 128k-byte flash memory or EPROM. 

Output pin as part of Boot PROM (or Flash) address bus 

after PCI reset. 

Input pin as Aux. Power detect pin to detect if Aux. Power 

exists or not, when initial power-on or PCI reset is asserted. 

Besides connecting this pin to Boot PROM, it should be 

pulled high to the Aux. Power via a resistor to detect Aux. 

power. If this pin is not pulled high to Aux. Power, the 

RTL8139C(L) assumes that no Aux. power exists. To 

support wakeup from ACPI D3cold or APM power-down, 

MA6/9356SEL 57 I/O 

this pin must be pulled high to Aux. power via a resistor. 

When this pin is pulled high with a 10K resistor, the 93C56 

EEPROM is used to store the resource data and CIS for the 

RTL8139C(L). The RTL8139C(L) latches the status of this 

pin at power-up to determine what EEPROM (93C46 or 

93C56) is used, afterwards, this pin is used as MA6. 

MA2/EESK 49 

O The MA2-0 pins are switched to EESK, EEDI, EEDO in 

MA1/EEDI 48 

O 93C46 (93C56) programming or auto-load mode. 

MA0/EEDO 47 

O,I 

EECS 50 O 93C46 (93C56) chip select 

MD0-7 108,107, 

105-100 

I/O Boot PROM data bus 

ROMCSB 110 O ROM Chip Select: This is the chip select signal of the 

Boot PROM. 

OEB 88 O Output Enable: This enables the output buffer of the Boot 

PROM or Flash memory during a read operation. 

WEB 89 O Write Enable: This signal strobes data into the Flash 

memory during a write cycle. 

Test and Other Pins 


RTT2-3 81, 82 TEST Chip test pins. 

RESET 84 I/O This pin must be pulled low by a 1.7K resistor. 

NC 54, 71, 72, 

73, 94 

- Reserved 

84



Power Pins 


VDD 

1, 12, 25, 35, 

46, 58, 59, 

106, 109, 119 

P Digital Power +3.3V 

77, 90, 96 P Analog Power +3.3V 

GND 7, 18, 30, 40, 

55, 56, 62, 

111, 112, 

113, 124 

P Digital Ground 

74, 80, 85, 93 P Analog Ground 

LED Interface 


LED0,1,2 99, 98, 97 O LED pins 

LEDS1-0 00 01 10 11 

LED0 Tx/Rx Tx/Rx Tx Tx 

LED1 LINK100 LINK10/100 LINK10/100 LINK100 

LED2 LINK10 FULL Rx LINK10 

During power down mode, the LEDs are OFF 

Attachment Unit Interface 


TXD+, TXD- 92, 91 O 100/10BASE-T transmit (Tx) Data 

RXIN+ 

RXIN- 

87, 86 I 100/10BASE-T receive (Rx) Data 

X1 79 I 25 MHz Crystal/OSC. Input 

X2 78 O Crystal Feedback Output: This output is used in crystal 

connection only. It must be left open when X1 is driven 

with an external 25 MHz oscillator. 

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85

5.5 PCI4410 PCMCIA Controller 

Power-Supply Terminals 

Name Type Description 

GND Device ground terminals 

VCC Power-supply terminal for core logic (3.3 V) 

VCCB Clamp voltage for PC Card interface. Matches card signaling 

environment, 5 V or 3.3 V. 

VCCI 

Clamp voltage for miscellaneous I/O signals (MFUNC, GRST#, and 

SUSPEND#) 

VCCL Clamp voltage for 1394 link function 

VCCP Clamp voltage for PCI interface, ZV interface, SPKROUT, INTA#, 

INTB# LED_SKT,VCCD0#, VCCD1#, VPPD0, VPPD1 

PC Card Power-Switch Terminals 


VCCD0# 

O Logic controls to the TPS2211 PC Card power-switch interface to 

VCCD1# 

VPPD0 

VPPD1 

O 

control AVCC 

Logic controls to the TPS2211 PC Card power-switch interface to 

control AVPP 

PCI System Terminals 


GRST# 

I Global reset. When global reset is asserted, GRST# causes the 

PCLK 

PRST# 

PCI4410A device to place all output buffers in a high-impedance 

state and reset all internal registers. When GRST# is asserted, the 

device is completely in its default state. For systems that require 

wake-up from D3, GRST# normally is asserted only during initial 

boot. PRST# should be asserted following initial boot so that PME 

context is retained when transitioning from D3 to D0. For systems 

that do not require wake-up from D3, GRST# should be tied to PRST. 

When the SUSPEND mode is enabled, the device is protected from 

GRST#, and the internal registers are preserved. All outputs are 

placed in a high-impedance state, but the contents of the registers are 

preserved. 

I PCI bus clock. PCLK provides timing for all transactions on the PCI 

I 

bus. All PCI signals are sampled at the rising edge of PCLK. 

PCI bus reset. When the PCI bus reset is asserted, PRST# causes the 

PCI4410A device to place all output buffers in a high-impedance 

state and reset internal registers. When PRST is asserted, the device is 

completely nonfunctional. After PRST# is deserted, the PCI4410A 

device is in a default state. When SUSPEND# and PRST# are 

asserted, the device is protected from PRST# clearing the internal 

registers.All outputs are placed in a high-impedance state, but the 

contents of the registers are preserved. 


PCI Address and Data Terminals 


AD[0:31[ I/O PCI address/data bus. These signals make up the multiplexed PCI 

address and data bus on the primary interface. During the address 

phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit 

address or other destination information. During the data phase, 

AD31–AD0 contain data. 

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C/BE[0:3]# I/O PCI bus commands and byte enables. These signals are multiplexed 

on the same PCI terminals. During the address phase of a primary bus 

PCI cycle, C/BE3#–C/BE0# define the bus command. During the data 

phase, this 4-bit bus is used as byte enables. The byte enables 

determine which byte paths of the full 32-bit data bus carry 

meaningful data. C/BE0# applies to byte 0 (AD7–AD0), C/BE1# 

applies to byte 1 (AD15–AD8), C/BE2# applies to byte 2 

(AD23–AD16), and C/BE3# applies to byte 3 (AD31–AD24). 

PAR I/O PCI bus parity. In all PCI bus read and write cycles, the PCI4410A 

device calculates even parity across the AD31–AD0 and 

C/BE3#–C/BE0# buses. As an initiator during PCI cycles, the 

PCI4410A device outputs this parity indicator with a one-PCLK 

delay. As a target during PCI cycles, the calculated parity is compared 

to the initiator’s parity indicator. A compare error results in the 

assertion of a parity error (PERR#). 

PCI Interface Control Terminals 


DECSEL# I/O PCI device select. The PCI4410A device asserts DEVSEL# to claim a 

PCI cycle as the target device. As a PCI initiator on the bus, the 

PCI4410A device monitors DEVSEL# until a target responds. If no 

target responds before timeout occurs, the PCI4410A device 

terminates the cycle with an initiator abort. 

FRAME# I/O PCI cycle frame. FRAME# is driven by the initiator of a bus cycle. 

FRAME# is asserted to indicate that a bus transaction is beginning, 

and data transfers continue while this signal is asserted. When 

FRAME# is deasserted, the PCI bus transaction is in the final data 

phase. 

GNT# I PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the 

PCI4410A device access to the PCI bus after the current data 

transaction has completed. GNT# may or may not follow a PCI bus 

request, depending on the PCI bus parking algorithm. 

IDSEL# I Initialization device select. IDSEL# selects the PCI4410A device 

during configuration space accesses. IDSEL# can be connected to one 

of the upper 24 PCI address lines on the PCI bus. 

86


PCI Interface Control Terminals (Continued) 


IRDY# I/O PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to 

complete the current data phase of the transaction. A data phase is 

completed on a rising edge of PCLK, when both IRDY# and TRDY# 

are asserted. Until IRDY# and TRDY# are both sampled asserted, 

wait states are inserted. 

PERR# I/O PCI parity error indicator. PERR# is driven by a PCI device to 

indicate that calculated parity does not match PAR when PERR# is 

enabled through bit 6 (PERR_EN) of the command register (PCI 

offset 04h, see Section 4.4). 

REQ# O PCI bus request. REQ# is asserted by the PCI4410A device to request 

access to the PCI bus as an initiator. 

SERR# O PCI system error. SERR# is an output that is pulsed from the 

PCI4410A device when enabled through bit 8 (SERR_EN) of the 

command register (PCI offset 04h, see Section 4.4) indicating a 

system error has occurred. The PCI4410A device need not be the 

target of the PCI cycle to assert this signal. When SERR# is enabled 

in the command register, this signal also pulses, indicating that an 

address parity error has occurred on a CardBus interface. 

STOP# I/O PCI cycle stop signal. STOP# is driven by a PCI target to request the 

initiator to stop the current PCI bus transaction. STOP# is used for 

target disconnects and is commonly asserted by target devices that do 

not support burst data transfers. 

TRDY# I/O PCI target ready. TRDY# indicates the primary bus target’s ability to 

complete the current data phase of the transaction. A data phase is 

completed on a rising edge of PCLK, when both IRDY# and TRDY# 

are asserted. Until both IRDY# and TRDY# are asserted, wait states 

are inserted. 

Multifunction and Miscellaneous Terminals 


INTA# O Parallel PCI interrupt. INTA# 

INTB# O Parallel PCI interrupt. INTB# 

LED_SKT O PC Card socket activity LED indicator. LED_SKT provides an output 

indicating PC Card socket activity. 

MFUNC0 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI 

interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV 

switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. 

See Section 4.32, Multifunction Routing Register, for configuration 

details. 


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MFUNC1 I/O Multifunction terminal 1. MFUNC1 can be configured as GPI1, 

GPO1, socket activity LED output, ZV switching outputs, CardBus 

audio PWM, GPE#, or a parallel IRQ. See Section 4.32, 

Multifunction Routing Register, for configuration details. 

Serial data (SDA). When VCCD0# and VCCD1# are high after a PCI 

reset, the MFUNC1 terminal provides the SDA signaling for the serial 

bus interface. The two-terminal serial interface loads the subsystem 

identification and other register defaults from an EEPROM after a 

PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for 

details on other serial bus applications. 

MFUNC2 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI 

DMA request, GPI2, GPO2, ZV switching outputs, CardBus audio 

PWM, GPE#, RI_OUT#, or a parallel IRQ. See Section 4.32, 


MFUNC3 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel 

IRQ or the serialized interrupt signal IRQSER. See Section 4.32, 


MFUNC4 I/O Multifunction terminal 4. MFUNC4 can be configured as PCI 

LOCK#, GPI3, GPO3, socket activity LED output, ZV switching 

outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. 

See Section 4.32, Multifunction Routing Register, for configuration 

details. Serial clock (SCL). When VCCD0# and VCCD1# are high 

after a PCI reset, the MFUNC4 terminal provides the SCL signaling 

for the serial bus interface. The two-terminal serial interface loads the 

subsystem identification and other register defaults from an EEPROM 

after a PCI reset. See Section 3.6.1, Serial Bus Interface 

Implementation, for details on other serial bus applications. 

MFUNC5 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI 

DMA grant, GPI4, GPO4, socket activity LED output, ZV switching 

outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section 

4.32, Multifunction Routing Register, for configuration details. 

MFUNC6 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI 

CLKRUN# or a parallel IRQ. See Section 4.32, Multifunction 

Routing Register, for configuration details. 

RI_OUT#/PME# O Ring indicate out and power-management event output. Terminal 

provides an output for ring-indicate or PME# signals. 

SPKROUT O Speaker output. SPKROUT is the output to the host system that can 

carry SPKR# or CAUDIO through the PCI4410A device from the PC 

Card interface. SPKROUT is driven as the exclusive-OR combination 

of card SPKR#//CAUDIO inputs. 

SUSPEND# I Suspend. SUSPEND# protects the internal registers from clearing 

when the GRST or PRST signal is asserted. See Section 3.8.4, 

Suspend Mode, for details. 

87


16-Bit PC Card Address and Data Terminals 


ADDR[0:25] O PC Card address. 16-bit PC Card address lines. ADDR25 is the most 

significant bit 

DATA[0:15] I/O PC Card data. 16-bit PC Card data lines. DATA15 is the most 

significant bit. 

16-Bit PC Card Interface Control Terminals 


BVD1 

(STSCHG#/RI#) 

BVD2 

(SPKR#) 

CD1# 

CD2# 

I 

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC 

Cards that include batteries. BVD1 is used with BVD2 as an 

indication of the condition of the batteries on a memory PC Card. 

Both BVD1 and BVD2 are high when the battery is good. When 

BVD2 is low and BVD1 is high, the battery is weak 

and should be replaced. When BVD1 is low, the battery is no longer 

serviceable and the data in the memory PC Card is lost. See Section 

5.6, ExCA Card Status-Change-Interrupt Configuration Register, for 

enable bits. See Section 5.5, ExCA Card Status-Change Register, and 

Section 5.2,ExCA Interface Status Register, for the status bits for this 

signal. Status change. STSCHG# is used to alert the system to a 

change in the READY, write protect, or battery voltage dead 

condition of a 16-bit I/O PC Card. Ring indicate. R# is used by 16-bit 

modem cards to indicate a ring detection. 

I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC 

Cards that include batteries. BVD2is used with BVD1 as an 

indication of the condition of the batteries on a memory PC Card. 

Both BVD1and BVD2 are high when the battery is good. When 

BVD2 is low and BVD1 is high, the battery is weak and should be 

replaced. When BVD1 is low, the battery is no longer serviceable and 

the data in the memory PC Card is lost. See Section 5.6, ExCA Card 

Status-Change-Interrupt Configuration Register, for enable bits. See 

Section 5.5, ExCA Card Status-Change Register, and Section 5.2, 

ExCA Interface Status Register, for the status bits for this signal. 

Speaker. SPKR# is an optional binary audio signal available only 

when the card and socket have been configured for the 16-bit I/O 

interface. The audio signals from cards A and B are combined by the 

PCI4410A device and are output on SPKROUT.DMA request. BVD2 

can be used as the DMA request signal during DMA operations to a 

16-bit PC Card that supports DMA. The PC Card asserts BVD2 to 

indicate a request for a DMA operation. 

I Card detect 1 and Card detect 2. CD1# and CD2# are connected 

internally to ground on the PC Card. When a PC Card is inserted into 

a socket, CD1# and CD2# are pulled low. For signal status, see 

Section 5.2, ExCA Interface Status Register. 


CE1# 

CE2# 


O Card enable 1 and card enable 2. CE1# and CE2# enable even- and 

odd-numbered address bytes. CE1#enables even-numbered address 

bytes, and CE2# enables odd-numbered address bytes. 

INPACK# I Input acknowledge. INPACK# is asserted by the PC Card when it 

can respond to an I/O read cycle at the current address.DMA request. 

INPACK# can be used as the DMA request signal during DMA 

operations from a 16-bit PC Card that supports DMA. If it is used as a 

strobe, the PC Card asserts this signal to indicate a request for a DMA 

operation. 

IORD# O I/O read. IORD# is asserted by the PCI4410A device to enable 16-bit 

I/O PC Card data output during host I/O read cycles. DMA write. 

IORD# is used as the DMA write strobe during DMA operations from 

a 16-bit PC Card that supports DMA. The PCI4410A device asserts 

IORD# during DMA transfers from the PC Card to host memory. 

IOWR# O I/O write. IOWR# is driven low by the PCI4410A device to strobe 

write data into 16-bit I/O PC Cards during host I/O write cycles. 

DMA read. IOWR# is used as the DMA write strobe during DMA 

operations from a 16-bit PC Card that supports DMA. The PCI4410A 

device asserts IOWR during transfers from host memory to the PC 

Card. 

OE# O Output enable. OE# is driven low by the PCI4410A device to enable 

16-bit memory PC Card data output during host memory read cycles. 

READ 

IREQ# 

DMA terminal count. OE# is used as terminal count (TC) during 

DMA operations to a 16-bit PC Card that supports DMA. The 

PCI4410A device asserts OE# to indicate TC for a DMA write 

operation. 

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I Ready. The ready function is provided by READY when the 16-bit 

PC Card and the host socket are configured for the memory-only 

interface. READY is driven low by the 16-bit memory PC Cards to 

indicatethat the memory card circuits are busy processing a previous 

write command. READY is driven high when the 16-bit memory PC 

Card is ready to accept a new data-transfer command. Interrupt 

request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the 

host that a device on the 16-bit I /O PC Card requires service by the 

host software. IREQ# is high (deasserted) when no interrupt is 

requested. 

88


16-Bit PC Card Interface Control Terminals (Continued) 


REG# 

O Attribute memory select. REG# remains high for all common 

memory accesses. When REG# is asserted, access is limited to 

attribute memory (OE# or WE# active) and to the I/O space (IORD# 

or IOWR# active). Attribute memory is a separately accessed section 

of card memory and generally is used to record card capacity and 

other configuration and attribute information. DMA acknowledge. 

REG is used as a DMA acknowledge (DACK#) during DMA 

operations to a 16-bit PC Card that supports DMA. The PCI4410A 

device asserts REG# to indicate a DMA operation. REG# is used in 

conjunction with the DMA read (IOWR#) or DMA write (IORD#) 

strobes to transfer data. 

RESET O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. 

WAIT# I Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the 

completion of the memory or I/O cycle in progress. 

WE# O Write enable. WE# is used to strobe memory write data into 16-bit 

memory PC Cards. WE# also is used for memory PC Cards that 

employ programmable memory technologies. DMA terminal count. 

WE# is used as TC during DMA operations to a 16-bit PC Card that 

supports DMA. The PCI4410A device asserts WE to indicate TC for 

WP 

IOIS16# 

VS1# 

VS2# 

a DMA read operation. 

I Write protect. WP applies to 16-bit memory PC Cards. WP reflects 

the status of the write-protect switch on 16-bit memory PC Cards. For 

16-bit I/O PC cards, WP is used for the 16-bit port (IOIS16#) 

function. I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. 

IOIS16# is asserted by the 16-bit PC Card when the address on the 

bus corresponds to an address to which the 16-bit PC Card responds, 

and the I/O port that is addressed is capable of 16-bit accesses. 

DMA request. WP can be used as the DMA request signal during 

DMA operations to a 16-bit PC Card that supports DMA. If used, the 

PC Card asserts WP to indicate a request for a DMA operation. 

I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in 

conjunction with each other, determine the operating voltage of the 

PC Card. 


CardBus PC Card Interface System Terminals 


CCLK O CardBus clock. CCLK provides synchronous timing for all 

transactions on the CardBus interface. All signals except CRST#, 

CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#, 

CVS2, and CVS1 are sampled on the rising edge of CCLK, and all 

timing parameters are defined with the rising edge of this signal. 

CCLK operates at the PCI bus clock frequency, but it can be stopped 

CCLKRUN# I/O 

CRST# O 

in the low state or slowed down for power savings. 

CardBus clock run. CCLKRUN# is used by a CardBus PC Card to 

request an increase in the CCLK frequency, and by the PCI4410A 

device to indicate that the CCLK frequency is going to be decreased. 

CardBus reset. CRST# brings CardBus PC Card-specific registers, 

sequencers, and signals to a known state. When CRST# is asserted, 

all CardBus PC Card signals are placed in a high-impedance state, 

and the PCI4410A device drives these signals to a valid logic level. 

Assertion can be asynchronous to CCLK, but deassertion must be 

synchronous to CCLK. 

CardBus PC Card Address and Data Terminals 


CAD[0:31] I/O CardBus address and data. These signals make up the multiplexed 

CardBus address and data bus on the CardBus interface. During the 

address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit 

address. During the data phase of a CardBus cycle, CAD31–CAD0 

CC/BE[0:3]# I/O 

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CPAR I/O 

contain data. CAD31 is the most significant bit. 

CardBus bus commands and byte enables. CC/BE3#–CC/BE0# are 

multiplexed on the same CardBus terminals. During the address phase 

of a CardBus cycle, CC/BE3#–CC/BE0# define the bus command. 

During the data phase, this 4-bit bus is used as byte enables. The byte 

enables determine which byte paths of the full 32-bit data bus carry 

meaningful data. CC/BE0# applies to byte 0 (CAD7–CAD0), 

CC/BE1# applies to byte 1 (CAD15–CAD8), CC/BE2# applies to 

byte 2 (CAD23–CAD16), and CC/BE3# applies to byte 3 

(CAD31–CAD24). 

CardBus parity. In all CardBus read and write cycles, the PCI4410A 

device calculates even parity across the CAD and CC/BE buses. As 

an initiator during CardBus cycles, the PCI4410A device outputs 

CPAR with a one-CCLK delay. As a target during CardBus cycles, 

the calculated parity is compared to the initiator’s parity indicator; a 

compare error results in a parity-error assertion. 

89


CardBus PC Card Interface Control Terminals 


CAUDIO I CardBus audio. CAUDIO is a digital input signal from a PC Card to 

the system speaker. The PCI4410A device supports the binary audio 

mode and outputs a binary signal from the card to SPKROUT. 

CBLOCK# I/O CardBus lock. CBLOCK# is used to gain exclusive access to a 

CCD1# 

CCD2# 

target. 

I CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are 

used in conjunction with CVS1 and CVS2 to identify card insertion 

and interrogate cards to determine the operating voltage and card 

type. 

CDEVSEL# I/O CardBus device select. The PCI4410A device asserts CDEVSEL# to 

claim a CardBus cycle as the target device. As a CardBus initiator on 

the bus, the PCI4410A device monitors CDEVSEL# until a target 

responds. If no target responds before timeout occurs, the PCI4410A 

device terminates the cycle with an initiator abort. 

CFRAME# I/O CardBus cycle frame. CFRAME# is driven by the initiator of a 

CardBus bus cycle. CFRAME# is asserted to indicate that a bus 

transaction is beginning, and data transfers continue while this signal 

is asserted. When CFRAME# is deasserted, the CardBus bus 

transaction is in the final data phase. 

CGNT# O CardBus bus grant. CGNT# is driven by the PCI4410A device to 

grant a CardBus PC Card access the CardBus bus after the current 

data transaction has been completed. 

CINT# I CardBus interrupt. CINT# is asserted low by a CardBus PC Card to 

CIRDY# I/O 

request interrupt servicing from the host. 

CardBus initiator ready. CIRDY indicates the CardBus initiator’s 

ability to complete the current data 

phase of the transaction. A data phase is completed on a rising edge 

of CCLK when both CIRDY and 

CTRDY are asserted. Until both CIRDY and CTRDY are sampled 

asserted, wait states are inserted. 

CPERR# I/O CardBus parity error. CPERR# reports parity errors during CardBus 

transactions, except during special cycles. It is driven low by a target 

two clocks following that data when a parity error is detected. 

CREQ# I CardBus request. CREQ# indicates to the arbiter that the CardBus 

PC Card desires use of the CardBus bus as an initiator. 

CSERR# I CardBus system error. CSERR# reports address parity errors and 

other system errors that could lead to catastrophic results. CSERR# is 

driven by the card synchronous to CCLK, but deasserted by a weak 

pull up, and may take several CCLK periods. The PCI4410A device 

can report CSERR# to the system by assertion of SERR# on the PCI 

interface. 


MiTac Secret 



CSTOP# I/O CardBus stop. CSTOP# is driven by a CardBus target to request the 

initiator to stop the current CardBus transaction. CSTOP# is used for 

target disconnects, and is commonly asserted by target devices 

do not support burst data transfers. 

CSTSCHG# I CardBus status change. CSTSCHG alerts the system to a change in 

the card’s status, and is used a wake-up mechanism. 

CTRDY# I/O CardBus target ready. CTRDY# indicates the CardBus target’s 

ability to complete the current data phase of the transaction. A data 

phase is completed on a rising edge of CCLK, when both CIRDY and 

CTRDY# are asserted; until this time, wait states are inserted. 

CVS1 

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and 

CVS2 

CVS2 are used in conjunction with CCD1# and CCD2# to identify 

card insertion and interrogate cards to determine the operating voltage 

and card type. 

IEEE 1394 PHY/Link Interface Terminals 


PHY_CTL1 

PHY_CTL0 

I/O PHY-link interface control. These bidirectional signals control 

passage of information between the PHY and link. The link can drive 

these terminals only after the PHY has granted permission, following 

a link request (LREQ). 

PHY_DATA[0:7] I/O PHY-link interface data. These bidirectional signals pass data 

between the PHY and link. These terminals are driven by the link on 

transmissions and are driven by the PHY on receptions. Only 

DATA1–DATA0 are valid for 100-Mbit speed. DATA4–DATA0 are 

valid for 200-Mbit speed and DATA7–DATA0 are valid for 400-Mbit 

speed. 

PHY_CLK I System clock. This input provides a 49.152-MHz clock signal for 

data synchronization. 

PHY_REQ O Link request. This signal is driven by the link to initiate a request for 

the PHY to perform some 

service. 

LINKON I 1394 link on. This input from the PHY indicates that the link should 

turn on. 

LPS O Link power status. LPS indicates that link is powered and fully 

functional. 

90


Zoomed-Video Interface Terminals 


ZV_HREF O Horizontal sync to the zoomed-video port 

ZV_VSYHC O Vertical sync to the zoomed-video port 

ZV_Y[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format 

ZV_UV[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format 

ZV_SCLK O Audio SCLK PCM 

ZV_MCLK O Audio MCLK PCM 

ZV_PCLK IO Pixel clock to the zoomed-video port 

ZV_LRCLK O Audio LRCLK PCM 

ZV-SDATA O Audio SDATA PCM 


MiTac Secret 


91

6. System Block Diagram 

U17 

PCMCIA/1394 Link 

U10 

Power 

Switch 

J507 

MINI PCI 

(wireless) 

PCMCIA/ 

CARDBUS 

Socket 

Controller 

PCI4410 

U515 

1394 PHY 

TSB41AB1 

MINI 1394 

LCD Panel 

TV S-Video 

CRT 

USB 

Cover Switch 

CDROM/DVD 

HDD 

U4 

NVIDIA 

NV17-MAP 

Audio DJ 


U6 

LAN PHY 

RTL8139CL 

RJ-45 Jack 

AGP Bus 4X 

PCI Bus 

U18 

USB2.0 

U1 

Pentium 4 CPU 

Willamette/Northwood 

Micro-FCPGA 478 pin 

U3 

Memory Controller 

Hub 

82845MCH-M 

U508 

Hub Link 

I/O Controller Hub 

82801CAM ICH3-M 

U510 

Flash ROM 

U502 

Thermal Sensor 

ADM1032 

AC Link U14 

U521 

Audio Codec Amplifier 

ALC202 

MiTac Secret 


IR Module 

Parallel Port 

U511 

LPC 

Super I/O 

PC87393 

ISA Bus 

U517 

Micro 

Controller 

H8/F3437 

200 pin DDR SO-DIMM Socket * 2 

J20 

M.D.C 

External Microphone 

Internal Microphone 

Internal Speaker 

SPDIF JACK 

RJ-11 Jack 

FAN 

Power Button 

Touch Pad 

Keyboard 

92

7. Maintenance Diagnostics 

7.1 Introduction 


Each time the computer is turned on, the system bios runs a series of internal checks on the hardware. 

This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error 

messages of post can alert you to the problems of your computer. 

If an error is detected during these tests, you will see an error message displayed on the screen. If the 

error occurs before the display is initialized,then the screen cannot display the error message. Error codes or 

system beeps are used to identify a post error that occurs when the screen is not available. 

The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test 

failed, the user can determine where the problem occurred by reading the last value written to port 378H by 

the 378H port debug board plug at PIO PORT. 

MiTac Secret 


93

7.2 Error Codes 

Code 

00h 

01h 

02h 

03h 

04h 

05h 

06h 

07h 

08h 

09h 

0Ah 

0Bh 

0Fh 

10h 

11h 

12h 


Following is a list of error codes in sequent display on the PIO debug board. 

POST Routine Description 

Boot started 

Disable A20 through A20 

Initialize chipset 

Test RAM 

Move BL into the RAM 

Execution in RAM 

User Flash Check 

Shadow system BIOS 

Checksum System BIOS ROM 

Proceed with Normal Boot 

Proceed with Crisis Boot 

Initialize Clock Sythesizer 

Fatal Error 

Some Type of Long Reset 

Turn Off Fasta20 for Post 

Signal Power On Reset 

Code 

13h 

14h 

15h 

16h 

17h 

18h 

19h 

1Ah 

1Bh 

1Ch 

1Dh 

1Eh 

1Fh 

20h 

21h 

22h 


Initialize the Chipset 

Search For ISA Bus VGA Adapter 

Reset Counter/Timer 1 

User Register Config Through CMOS 

Size Memory 

Dispatch to RAM Test 

Checksum the ROM 

Reset PIC’s 

Initialize Video Adapter 

Initialize Video(6845 Regs) 

MiTac Secret 


Initialize Color Adapter 

Initialize Monochrome Adapter 

Test 8237A Page Registers 

Test Keyboard 

Test Keyboard Controller 

Check If CMOS Ram Valid 

94


Code 

23h 

24h 

25h 

26h 

27h 

28h 

29h 

2Ah 

2Bh 

2Ch 

2Dh 

2Eh 

2Fh 

30h 

31h 

32h 




Test Battery Fail & CMOS X-SUM 

Test DMA Controller 

Initialize 8237A Controller 

Initialize Int Vectors 

RAM Quick Sizing 

Protected mode entered safely 

RAM Test Completed 

Protected mode exit successful 

Setup Shadow 

Going to Initialize Video 

Search For Monochrome Adapter 

Search For Color Adapter 

Signal Messages Displayed 

Special Into of Keyboard Controller 

Test If Keyboard Present 

Test Keyboard Interrupt 

Code 

13h 

14h 

15h 

16h 

17h 

18h 

19h 

1Ah 

1Bh 

1Ch 

1Dh 

1Eh 

1Fh 

20h 

21h 

22h 


Initialize the Chipset 

Search For ISA Bus VGA Adapter 

Reset Counter/Timer 1 

User Register Config Through CMOS 

Size Memory 

Dispatch to RAM Test 

Checksum the ROM 

Reset PIC’s 

Initialize Video Adapter 

Initialize Video(6845 Regs) 

MiTac Secret 


Initialize Color Adapter 

Initialize Monochrome Adapter 

Test 8237A Page Registers 

Test Keyboard 

Test Keyboard Controller 

Check If CMOS Ram Valid 

95


Code 

33h 

34h 

35h 

36h 

37h 

38h 

39h 

3Ah 

3Bh 

3Ch 

3Dh 

3Eh 

3Fh 

40h 

41h 

42h 




Test Keyboard Command Byte 

TEST, Blank and Count All RAM 

Protected mode entered safely 

RAM Test Complete 

Protected mode exit successful 

Update Output Port 

Setup Cache Controller 

Test If 18.2Hz Periodic Working 

Test for RTC ticking 

Initialize the Hardware Vectors 

Search and Init the Mouse 

Update NumLock Status 

Special init of COMM and LPT ports 

Configure the COMM and LPT ports 

Initialize the floppies 

Initialize the Hard Disk 

Code 

43h 

44h 

45h 

46h 

47h 

48h 

49h 

99h 


Initialize option ROMs 

OEM’s init of power management 

Update NumLock Status 

Test For Coprocessor Installed 

OEM Function Before Boot 

Dispatch To Op.Sys.Boot 

Jump Into Bootstrap Code 

Resume SMRAM not Found 

MiTac Secret 


96

7.3 Maintenance Diagnostics 

7.3.1 Diagnostic Tools : 

LED * 8 

PIO CONNECTOR * 1 

7.3.2 Circuit: 

PIO 

Connector 

LED 

25 

13 


14 

1 

OR 

P/N:411904800001 

Description: PWA; PWA-378Port Debug BD 

Note: Order it from MIC/TSSC 

PIN1 : STROBE PIN 13 : SLCT 

MiTac Secret 


PIN10: ACK# PIN 16 : INT# 

PIN11: BUSY PIN 17 : SELIN# 

PIN12: PTERR PIN 14 : AUTOFD# 

PIN{9:2}: PD{7:0} 

97

8. Trouble Shooting 

8.1 No Power 

8.2 No Display 

8.3 VGA Controller Failure LCD No Display 

8.4 External Monitor No Display 

8.5 Memory Test Error 

8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error 

8.7 Hard Driver Test Error 

8.8 CD-ROM Driver Test Error 

8.9 PIO Port Test Error 

8.10 USB Port Test Error 

8.11 Audio Failure 

8.12 LAN Test Error 

8.13 PC Card Socket and IEEE1394 Failure 


MiTac Secret 


98

8.1 No Power 

No power 

Is the 

notebook connected 

to power (either AC adaptor 

or battery)? 

Try another known good 

battery or AC adapter. 

Power 

OK? 

No 

Is the 

M/B and charger 

BD connected 

properly? 

No 

Try another known 

good charger BD. 


When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. 

Yes 

Yes 

No 

Connect AC adaptor 

or battery. 

Replace the faulty 

AC adaptor or 

Battery. 

Connect AC adaptor 

or battery. 

Power 

OK? 

Yes 


Charger BD. 

No 

Board-level 

Troubleshooting 

Where from 

power source problem 

(first use AC to 

power it)? 

Battery 

AC 

Power 

MiTac Secret 


Replace 

Motherboard 

Check following parts and signals: 

Parts: Signals: 

J19 

PF503 

PF1 

PL16 

PL17 

PQ12 

PQ9 

PD506 

PD508 

PU21 

PU15 

PU12 

PU18 

PU20 

PU22 

J18 

U517 

PU506 

PQ14 

ADINP 

ALWAYS 

DVMAIN 

+5VA 

Check following parts and signals: 


PU24 

PU508 

PQ511 

PF501 

PF502 

PL505 

PL506 

PL507 

DBATT 

-ADEN 

BAT_V 

BAT_T 

99

8.1 No Power 

P26 

ADINP_1 

P26 

ADINP_2 

POWER IN 

J19 P26 

P25 

+5V 



PF503,PF1 

PL16,PL17 

PQ9, PQ12 

P26 

NOTE : 

P26 

PF503 

PQ15 

JL3 

JL1 

PD508 

ALWAYS 

+5VA 

P22 

PU506 

P26 

ADINP 

Main Voltage Map 

PD15,PD16,PD17 

L521 

PQ8 

PU23 

: Page 26 on M/B Board 

circuit diagram. 

: Through by part PF503. 

P22 

+5VAS 

P22 

+3VA 

Charge 

PU21,PU15 

PU12,PU18,PU20 

P20 

H8_VDD5 

PD506 

Discharge 

D9 

DVMAIN 

P13 

P23 

DBATT 

P26 

VCC_RTC 

PU24,PU508 

PQ511,PQ13 

Discharge 

PL2 

PL501,PL502,PU509,PU510 

PU1~PU5,PU501~PU504 

PL4,PU7~PU9 

PL3,PD21,PD22 

PL504 

PU507 

D/VMAIN_P1 

PU511,PU14 

PL5~PL7 

PU512,PU17 

PT1,PD11 

PL13,PL15 

PL14 

P25 

+5V_CD 

P25 

+12V 

P25 

+3V 

P25 

+5V 

P24 

CPU_CORE 

PQ5 

PU502,PU503,PL503 

PU501 PU3,PU5,PL502 

Q3,L9 

D507 

L514 

L518 

PU11 

U10 

U10 

PU10 

PU19 

P26 

+12VS 

AVDDAD 

+5V_AMP 

1394AVDD 

+3V_LAN 

P26 

VCCA 

VCCP 

+3V_ICH 

P26 

P17 

P17 

+5VS 

P15 

P16 

+3VS 

P15 

P15 

P22 

U2 

+1.5V 

DDR_2.5V 

MiTac Secret 


L21 

PU505 

P16 

AVDD_LAN 

P22 

+1.8V_ICH 

P5 

VCCPVID 

PQ16 

PU6 

PU2 

PU1 

P22 

+1.35VS 

+1.5VS 

+1.8VS 

VDD_MEM2.5 

D/D Board 

L16 

L16 

L17 

L18 

L19 

L506 

Q11 

PU6 

L506 

Q10 

REF_1.25V 

P8 

+3VCLK66 

P8 

+3VCLKCPU 

P8 

+3VCLKANA 

P8 

+3VCLKPCI 

P11 

A3V 

P21 

3V_USB 

P22 

+2.8VS 

25V_USB 

P27 

P21 

VCC3_IR 

100

POWER IN 

U517 

J19 

Micro 

Controller 

H8/F3437 

-SUSB 

P20 

8.1 No Power 

3 

4 

12 

14 

58 



1 

2 

S 

PC531 

0.1µ 

LEARNING 

PWR_ON 

ADJ_ON 

PF503 

PF1 

PC77 

1µ 

PR538 

0 

+12V +12VS 

From U508 ICH3-M 

+12V +12VS 

PR526 

1M 

PR525 

1M 

PQ5 

SI2303DS 

G 

D 

PQ508 

2N7002 

PC69 

0.1µ 

8 

7 

6 

5 

D 

PC67 

0.1µ 

PR540 

1M 

PC58 

0.1µ 

3 

2 

1 

PL16 

120Z/100M 

PL17 

120Z/100M 

PC62 

0.1µ 

PQ510 

2N7002 

+3V +3VS 

PR44 

470K 

Mother Board 

PC78 

0.1µ 

PR549 

470K 

PR543 

0 

PD509 

RLZ24D 

PR552 

470K 

1 

2 

3 

S 

3 

2 

1 

G 

S 

JO27,JO28 

D 

G 

D 

8 

7 

6 

5 

PQ12 

SI4835DY 

PQ9 

SI4835DY 

5 

6 

7 

8 

PR69 

.08 

PR68 

.08 

DVMAIN 

PL504 

PC552 

0.1µ 

PC526 

22µ 

JL3 

JL1 

PC529 

0.1µ 

PR548 

4.7K 

MiTac Secret 


+3V +3VS +5V +5VS 

PU19 

SI4800DY 

G 

S 

PC48 

1000P 

8 

7 

6 

5 

D 

PU11 

SI4800DY 

3 

2 

1 

+5V +5VS 

G 

PC36 

1000P 

S 

+5VA 

PR37 

470K 

PL4 

PQ3 

2N7002 

PC32 

22µ 

PR38 

470K 

PQ4 

2N7002 

PC31 

0.1µ 

ADINP 

ADINP_1 

ADINP_2 

PR539 

4.7K 

PR555 

10 

PR542 

1K 

PR557 

1K 

PR31 

10K 

PC556 

0.1µ 

PD15 

PD16 

PD17 

22 

23 

7 

28 

PD508 

BAV70LT1 

V+ 

SHDN 

PC547 

0.1µ 

P25 

2 

1 

2 

1 

PD506 

BAV70LT1 

PU507 

MAX1632 

TIME/ON5 

RUN/ON3 

PC544 

1000P 

System Power (3V, 5V, 12V) 

Audio DJ Power (+5V_CD) 

1 

16 

3 

VIN 

FPWM 

EN 

P25 

PU9 

FAN5234 

3 

3 

ALWAYS 

DVMAIN 

+3V 

+5V 

+12V 

+5V_CD 

101

P20 

U517 

Micro 

Controller 

H8/F3437 

ADINP 

ADINP_1 

ADINP_2 

8.1 No Power 

44 

40 

47 

19 



CHG_I 

PR52 

10 

PR51 

10 

I_LIMIT 

-BATT_DEAD 

SW_+5VA 

PR62 

0 

PR547 

0 

+3VA 

PC49 

1µ 

PC56 

1µ 

PC76 

10µ 

PC553 

10µ 

PL12 

PL9 

PR29 

0 

PC50 

1µ 

PR47 

100K 

PR46 

49.9K 

PC68 

0.1µ 

PC551 

0.1µ 

Q507 

DTC144TKA 

PR537 

12.1K 

R1 

1 

27 

26 

13 

15 

14 

28 

DCIN 

CSSP 

CSSN 

REFIN 

VCTL 

ICTL 

IINP 

PU21 

MAX1772 

BATT_DEAD 

P23 

BST 

DHI 

LX 

DL0V 

DL0 

PGND 

CSIP 

CSIN 

BATT 

PR63 

100K 

1 

25 

24 

23 

22 

21 

20 

19 

18 

17 

PU22A 

LMV393M 

+5VAS 

8 

4 

+ 

_ 

PC550 

0.1µ 

3 

2 

PC59 

0.1µ 

PD13 

EC31QS03L 

PL10 PL11 

PC42 

22µ 

PD507 

BAW56 

1 

2 

DVMAIN 

PR64 

475K 

PR59 

100K 

3 

PD14 

EC31QS03L 

PU15 

SI4800DY 

PU12 

SI4832DY 

5 

6 

7 

8 

G 

D 

S 

1 

2 

3 

5 

6 

7 

8 

G 

D 

S 

1 

2 

3 

PR544 

4.7K 

+5VAS 

PQ6 

SW_+5VA 

ALWAYS 

PR54 

12.1K 

JS506 

PC537 

0.1µ 

PD10 

EC31QS03L 

DBATT 

PL8 

10UH 

PR53 

402K 

PR49 

53.2K 

3 

SHUTDN 

6 

5VTAP 

7 

F/B 

8 

IN 

MiTac Secret 


PC40 

0.1µ 

5V Resume Power 

5 

6 

PC53 

0.1µ 

PU506 

LP2951 

PR536 

1 

PR42 

.035 

PC549 

0.1µ 

+5VAS PR545 

1M 

+ 

_ 

8 

4 

P22 

SENSE 

OUT 

7 

PU22B 

LMV393M 

2 

1 

PD505 

UDZS5.6B 

PQ14 

DTC144WK 

PR535 

1 

PC548 

0.1µ 

8 

7 

6 

5 

D 

PU18 

SI4835DY 

LI_OVP 

+5VA 

G 

PC533 

0.1µ 

S 

PC530 

0.1µ 

PL503 

120Z/100M 

3 

2 

1 

3 

2 

1 

PC21 

10µ 

PU20 

SI4835DY 

8 

7 

6 

5 

S 

PR530 

1M 

PQ509 

2N7002 

S 

G 

G 

D 

PR524 

470K 

D 

PQ15 

SI2301DS 

+5V 

PC61 

10µ 

+5VA 

DBATT 

102

8.1 No Power 

P20 

U517 

Micro 

Controller 

H8/F3437 



+5VA 

PR65 

100K 

PQ11 

DTC144WK 

30 

38 

39 

99 

16 

1 

C700 

0.1µ 

PQ8 

SI2301DS 

S D 

G 

+5VA 

3 

R1 

2 

-ADEN 

D505 

BAV70LT1 

C701 

0.1µ 

+5VAS 

PD19 

BAS32L 

R668 

10K 

+3V 

+5VA 

ADINP 

R649 

10K 

BAT_TEMP 

BAT_VOLT 

BAT_CLK 

BAT_DATA 

DBATT 

PR558 

169K 

PR527 

47K*8 

RP529 

33*4 

+5VA 

PR71 

100K 

BAT_T 

BAT_V 

BAT_C 

BAT_D 

PQ511 

DTC144WK 

PC559 

0.1µ 

PR550 

301K 

PR551 

100K 

8 

7 

6 

5 

D 

PU508 

SI4835DY 

G 

PC554 

0.1µ 

S 

3 

2 

1 

PR72 

100K 

PQ13 

2N7002 

+5VAS 

PR531 

4.99K 

PR532 

20K 

PU24 

SI4835DY 

8 

7 

6 

5 

D 

G 

S 

PF501 

6.5A/32VDC 

PF502 

6.5A/32VDC 

MiTac Secret 


PC539 

1000P 

3 

2 

1 

PR70 

1M 

PC540 

0.1µ 

PL507 

120Z/100M 

PL506 

120Z/100M 

PL505 

120Z/100M 

PC546 

1000P 

VMAIN 

PC545 

0.1µ 

1,2 

3 

4 

5 

J18 

P22 

Battery Connector 

103


No Display 

Monitor 

or LCD module 

OK? 

Yes 

No 

Replace monitor 

or LCD. 


There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. 

Make sure that CPU module, 

DIMM memory are installed 

Properly. 

Display 

OK? 

No 

Yes 

1.Try another known good CPU 

module, DIMM module and BIOS. 

2.Remove all of I/O device (FDD, 

HDD, CD-ROM…….) from 

motherboard except LCD or monitor. 

Display 

OK? 

No 

Yes 

Correct it. 

Board-level 


Replace 

Motherboard 

System 

BIOS writes 

error code to port 

378H? 

MiTac Secret 


1. Replace faulty part. 

2. Connect the I/O device to the 

M/B one at a time to find out 

which part is causing the problem. 

No 

Check system clock and reset 

circuit. 

To be continued 

Clock and reset checking 

Yes 

Refer to port 378H 

error code description 

section to find out 

which part is causing 

the problem. 

104

116 


+3VS 

R120 

0 

CPU_CORE 

L17 

L19 

L18 

L16 

PCICLK_LAN 

PCICLK_CARD 

PCICLK_USB 

P15 U17 

PCMCIA 

Controller 

P16 U6 

LAN Controller 

120Z/100M 

120Z/100M 

120Z/100M 

120Z/100M 

J507 

P21 

109 

U18 

P21 

USB2.0 Hub 

+3VS 

R105 

10K 

Q6 

DTC144TKA 

R93 

8.2K 

MiniPCI 

Connector 

R599 

33 

R111 

33 

R112 

33 

+3VCLKCPU 

+3VCLKPCI 

+3VCLKANA 

+3VCLK66 

PCICLK_MINI 

C117 

22P 

C111 

22P 

-VTT_PWRGD 

4 

3 

2 

1 


****** System Clock Check ****** 

R596 

33 

28 

43 

46,50 

8,14 

1,26,37 

19,32 

11 

10 

17 

16 

2 

X3 

14.318MHz 

3 

P8 

U5 

Clock 

Generator 

ICS950805 

54 

52 

51 

45 

44 

21 

FS0 

R582 33 

R581 33 

R113 33 

R92 1K 

R584 33 

R583 33 

55 FS1 

40 FS2 R94 1K 

29 

30 

25 

34 

53 

39 

22 

5 

56 

12 

23 

SMBDATA 

SMBCLK 

-SUSA 

-STP_PCI 

-STP_CPU 

+3V_ICH 

R96 

8.2K 

R553 

49.9 1% 

R97 

8.2K 

+3VS 

R98 

1K 

R548 

49.9 1% 

R579 33 

R595 33 

R597 33 

R585 33 

R586 33 

R598 33 

R594 33 

FS2 FS1 FS0 CPUCLK 

0 0 1 100MHZ 

0 1 1 133MHZ 

R516 

49.9 1% 

HCLK_MCH 

-HCLK_MCH 

66M_MCH66IN 

MiTac Secret 


P6 

P7 

R515 

49.9 1% 

U3 

Memory 

Controller Hub 

82845MP 

USBCLK_ICH 

66M_ICH 

PCICLK_ICH 

14M_ICH 

SIO_14.318MHZ 

PCICLK_LPC 

66M_AGP 

HCLK_CPU 

-HCLK_CPU 

H_BSEL0 

CLK_DDR[0:5] 

-CLK_DDR[0:5] 

SMBDATA 

SMBCLK 

20 

8 

P4 

P19 

U1 

CPU 

Pentium 4 

J11, J502 

DDR SO-DIMM 

P13 

U508 

I/O 

Controller 

Hub 

82801CAM 

U511 

Super I/O 

P10 

U4 

NV17-MAP 

105

P24 

PU5 

LTC3716 


Power 

Module 

P25 

PU507 

LTC3716 

P20 

U517 

Micro 

Controller 

H8/F3437 


1 

36 

7 

28 

14 

1 

PR19 

1K 

PQ2 

2N7002 

PR542 

1K 

PR557 

1K 

PWR_ON 

18 -H8_ICH3BTN 

D 

-H8_RESET 1 

S 

+3VS 

PR543 

0 

H8_PWROK 

68 5 

G 

R47 

100K 

PQ1 

2N7002 

+5VA 

P20 

D 

S 

PR18 

1M 

23 -POWERBTN -POWERSW 

R673 

1K 

U518 

Level Shift 

RESET U524 

IMP811 

G 

SN74CBTD3384 

MN 

VCC 

4 

3 

4 

CPU_CORE_EN 

VR_PWRGD 

+3V_ICH 

R241 

10K 

C778 

0.01µ 


****** Power Good & Reset Circuit Check ****** 

D/D Board 

SW1 

+5VS 

R143 

4.7K 

PWROK 

+5VA CPU_CORE VCCPVID 

R1 

+5VS 

C34 

10µ 

Q520 

DTC144TKA 

U509 

MAX809 

R4 

56 

1 

VIN 

8 

EN 

4 

PG 

3 2 

VCC RESET# 

+3V 

R1 

Q505 

DTC144TKA 

P5 

U2 

TPS62003 

-RSMSRT 

-PWRBTN 

-THRMTRIP 

L 

FB 

9 

5 

L4 

10UH 

P13 

U508 

I/O 

Controller 

Hub 

ICH3 – M 

82801CAM 

VCCPVID 

C29 

10µ 

-PCIRST 

P10 U4 

NV17-MAP 

-AC_RST 

-PCIRST 

P6 

+3V_ICH 

R1 

U3 

MCH – M 

82845MP 

MiTac Secret 


-PCIRST_MSK 

-GATE1394 

-HDD_RST 

-CDROM_RST 

R629 

4.7K 

R19 

33 

+3V 

2 

Q7 

DTC144TKA 

1 

24 

1 

2 

5 

A 

9 

-CPURST 

H_PWRGD 

P19 U511 

Super I/O 

U512 

NC7S32 

+3V 

5 

VCC 

B Y 

B U13 A 

VCC NC7S08 Y 

J7 

P14 

U505 

Audio DJ 

4 

5 

4 

Primary EIDE 

Connector 

23 

-THRMTRIP 

VCC_CORE 

J20 

R34 

301 

111 

P21 U18 

USB2.0 Hub 

-PCIRST_N 

-CBRST 

MDC 

-CCDROM_RST 

25 

P16 

R121 

0 

R192 

33 

115 

P4 

U1 

CPU 

Pentium 4 

5 

26 

P21 J507 

MINI PCI 

P17 

P16 U6 

LANPHY 

U17 

CardBus 

P15 

J5 

110 

11 

U14 

ALC201 

P14 

Secondary EIDE Connector 

106

VGA Controller Failure 

LCD No Display 

1. Confirm LCD panel or monitor is good 

and check the cable are connected 

properly. 

2. Try another known good monitor or 

LCD module. 

Display 

OK? 

No 

Remove all the I/O device & cable from 

motherboard except LCD panel or extended 

monitor. 

Display 

OK? 

No 

Yes 

Yes 



There is no display or picture abnormal on LCD although power-on-self-test is passed. 

Replace faulty 

LCD or monitor. 

Connect the I/O device & cable 

to the M/B one at a time to find 

out which part is causing the 

problem. 

Board-level 


MiTac Secret 


Replace 

Motherboard 

Check if 

U4, J4 are cold 

solder? 

No 

Yes 

Re-soldering. 

One of the following parts on the mother-board may be 

defective, use an oscilloscope to check the following signal or 

replace the parts one at a time and test after each replacement. 


U3 

U4 

U508 

Q514 

Q2 

RP533 

Q518 

U523 

X1 

J9 

M/B 

J502 

L501 

L502 

L503 

L504 

J2 

D/D Board 

+3VS 

LCDVCC 

ENPVDD 

LCD_ID[0:3] 

TXOUT[0:3]+ 

TXOUT[0:3]- 

TXCLK+ 

TXCLK- 

-ENABKL_MSK 

ENPBLT 

BLADJ 

107

+3VS 

P7 

U3 

Memory 

Controller 

Hub 

82845MP-M 

P13 

R540 10K 

R49 10K 

R56 10K 

R54 10K 

R50 10K 

R51 10K 

U508 

I/O 

Controller 

Hub 

ICH3-M 



There is no display or picture abnormal on LCD although power-on-self-test is passed. 

R541 10K 

R52 10K 

R57 10K 

R55 10K 

AGP_AD[0:31] 

-AGP_CBE[0:3] 

-AGP_FRAME 

-AGP_IRDY, -AGP_TRDY 

-AGP_DEVSEL, -AGP_STOP 

AGP_ADSTB[0,1] 

-AGP_ADSTB[0,1] 

AGP_PAR 

-AGP_RBF, -AGP_WBF 

-AGP_PIPE 

-AGP_REQ 

-AGP_GNT 

AGP_ST[0:2] 

-ENABKL_MSK 

R799 

10K 

R1 

MSTRAPSEL3 

MSTRAPSEL2 

MSTRAPSEL1 

MSTRAPSEL0 

+5VS 

PAMCFG0 

PAMCFG1 

PAMCFG2 

PAMCFG3 

PCI_AD 

BUS_TYPE 

R95 

0 

Q518 

DTC144TKA 

ENPBLT 

U4 

VGA 

Controller 

NV17-MAP 

2 

1 

P10 P11 

C44 

0.1µ 

X1 

27MHZ 

3 

2 

4 

1 

+3VS 

+12VS 

ENPVDD 

TXOUT [0:3]+ 

TXOUT [0:3]- 

TXCLK+ 

TXCLK- 

C47 

18P 

C56 

18P 

R37 

470K 

8 

7 

6 

5 

D 

Q514 

NDS9410 

4 

23 

G 

P26 

S 

3 

2 

1 

Q2 

DTC144TKA 

R41 

10K 

J9 J502 

BLADJ 

C703 

0.1µ 

ENPBLT 

RP501 

10K*4 

C696 

10µ 

+5VS 

+5VAS 

+3VS 

DC Power Board 

L504 

L503 

L502 

L501 

Display 

LTN152W3 

& 

B152EW01 

LCD_ID0 

LCD_ID1 

LCD_ID2 

LCD_ID3 

MiTac Secret 


B 

A 

U523 

VCC 

P13 

Y 

5 

4 

+5VS 

ENPBLT1 

BLADJ 

From U517 H8 

4 

23 

C32 

1000P 

LCD_ID3 LCD_ID2 LCD_ID1 LCD_ID0 

C503 

0.1µ 

C31 

0.1µ 

0 

C504 

0.1µ 

C33 

1000P 

0 

LCDVCC 

RP533 

1K*4 

0 

2,3 

11 

4 

1 

5,6 

J2 

Inverter 

1 

1,2 

21 

23 

25 

27 

8,5,11,20 

6,7,13,18 

14 

12 

J4 

P12 

LCD Connector 

Inverter Board 

LCD 

108



There is no display or picture abnormal on CRT monitor, but it is OK for LCD. 

External Monitor No Display 

1. Confirm monitor is good and check 

the cable are connected properly. 

2. Try another known good monitor. 

Display 

OK? 

No 

Remove all the I/O device & cable from 

motherboard except monitor. 

Display 

OK? 

No 

Yes 

Yes 

Replace faulty monitor. 

Connect the I/O device & cable 

to the M/B one at a time to find 

out which part is causing the 

problem. 

Board-level 


No 

Yes 

Re-soldering. 

One of the following parts on the mother-board may be 

defective, use an oscilloscope to check the following signal or 

replace the parts one at a time and test after each replacement. 

Parts: 

U4 

J8 

L506 

Q501 

Q502 

FA501 

L507 

L508 

L509 

F502 

D502 

X1 

Check if 

U4, J8 

are cold solder? 

MiTac Secret 


Replace 

Motherboard 

Signals: 

+3VS 

A3V 

+5VS 

SDA 

HSYNC 

VSYN 

SCL 

RED 

GREEN 

BLUE 

109


P11 

U4 

VGA 

Controller 

NV17-MAP 

X1 

27MHZ 

3 

2 

1 

4 

C47 

18P 

C56 

18P 


There is no display or picture abnormal on CRT monitor, but it is OK for LCD. 

IFP0PLLVDD 

DACVDD 

PLLVDD 

DAC2VDD 

DVOVREF 

SDA 

HSYNC 

VSYNC 

SCL 

RED 

GREEN 

BLUE 

L5 

L8 

L11 

L515 

R64 

120Z/100M 

120Z/100M 

120Z/100M 

120Z/100M 

10K 

A3V 

R539 

2.2K 

L507 120Z/100M 

L508 120Z/100M 

L509 120Z/100M 

L506 

120Z/100M 

+3VS 

R527 

2.2K 

+3VS 

RP503 

75*4 

4 

3 

2 

1 

X 

5 

6 

7 

X 

8 

G 

S D 

Q501 

2N7002 

+5VS 

G 

S D 

Q502 

2N7002 

4 

5 

3 

6 

2 

7 

X 

1 

8 

X 

CP502 

22P*4 

FA501 

120OHM/100MHZ 

MiTac Secret 


CP503 

22P*4 

+5VS 

F502 

mircoSMDC110 

4 

3 

2 

1 

5 

6 

7 

8 

D502 

EC11FS2 

DDC2B 

C586 

10µ 

JL502 

JL501 

9 

12 

13 

14 

15 

1 

2 

3 

6,7,8,10 

J8 

P12 

External VGA Connector 

110


Extend DDRAM is failure or system hangs up. 

Memory Test Error 

1.If your system installed with expansion 

SO-DIMM module then check them for 

proper installation. 

2.Make sure that your SO-DIMM sockets 

are OK. 

3.Then try another known good SO-DIMM 

modules. 

Test 

OK? 

No 

Yes 

If your system host bus clock running at 

266MHZ then make sure that SO-DIMM 

module meet require of PC 266. 

Test 

Ok? 

No 

Yes 



DDRAM module. 


DDRAM module. 

Board-level 


Replace 

Motherboard 

One of the following components or signals on the motherboard 

may be defective ,Use an oscilloscope to check the signals or 

replace the parts one at A time and test after each replacement. 

Parts: 

Signals: 

U3 

U5 

J502 

J11 

RP17~RP21 

RP508~RP516 

RP5~RP17 

R108 

R118 

R582 

R581 

R113 

MiTac Secret 


DDR_2.5V 

MD[0:63] 

MA[0:12] 

MDQS[0:8] 

MCB[0:7] 

CKE[0:3] 

-CS[0:3] 

MEM_BS[0,1] 

-SRASA 

-SCASA 

-SWEA 

HCLK_MCH 

-HCLK_MCH 

66M_MCH66IN 

CLK_DDR[0:5] 

CLK_DDR[0:5]# 

SMBDATA 

SMBCLK 

111

P7 

U3 

Memory 

Controller 

Hub 

82845MP-M 


Extend DDRAM is failure or system hangs up. 

CKE [0:3], -CS [0:3] 

MDQS[0:8] 

MD [0:63] 

MEM_BS [0,1] 

MA [0:12], MCB [0:7] 

-SRASA, -SCASA, -SWEA 

DDR_REF 

C553 

1000P 

HCLK_MCH 

-HCLK_MCH 

66M_MCH66IN 

C559 

0.1µ 

DDR_2.5V 

R555 

150 

R554 

150 

R582 

33 

R581 

33 

R113 

33 

CLK_DDR [0:5] , CLK_DDR [0:5]# 

RP5~RP17 33*8 

R108, R118 10 

45 

44 

21 

U5 

Clock 

Generator 

ICS950805 


MDQSA [0:8] 

MDD [0:63] 

MEMA_BS [0,1] 

MAA [0:12], MCBA [0:7] 

R96 

P13 

8.2K 

From U508 ICH3-M 

SMBDATA 

P8 

-MSRAS, -MSCASA, -MSWEA 

SMBCLK 

+3V_ICH 

29 

30 

DDR_2.5V 

R97 

8.2K 

RP17~RP21 

RP508~RP516 

56*8 

DDR_2.5V 

MiTac Secret 


R117 

49.9 

R119 

49.9 

C160 

0.1µ 

CKE [0,1], -CS[0,1] 

CLK_DDR [0:2] , -CLK_DDR [0:2] 

C135 

1000P 

C137 

1000P 

REF_DIM 

C154 

0.1µ 

CKE [2,3], -CS[2,3] 

CLK_DDR [3:5] , -CLK_DDR [3:5] 

J502 

P9 

DDR SODIMM 

J11 

P9 

DDR SODIMM 

112



Error message of keyboard or touch-pad failure is shown or any key does not work. 

Keyboard or Touch-Pad 

Test Error 

Is K/B or 

T/P cable connected to 

notebook 

properly? 

Try another known good Keyboard 

or Touch-pad. 

Test 

Ok? 

Yes 

No 

Yes 

No 

Correct it. 


Keyboard or 

Touch-Pad 

Board-level 


Check 

U517, J15, J23 

for cold solder? 

MiTac Secret 


Replace 

Motherboard 

No 

Yes 

Re-soldering 

One of the following parts or signals on the motherboard 

may be defective, use an oscilloscope to check the signals 

or replace the parts one at a time and test after each 

replacement. 

Parts 

Signals 

U511 

U517 

U518 

L521 

R656 

X503 

L511 

L512 

L513 

J15 

J23 

+5VA 

H8_VDD51 

+3VS 

+5V 

-ROMCS 

-MCCS 

KI[0:7] 

KO[0:15] 

T_CLK 

T_DATA 

SA2 

IRQ1 

IRQ12 

-IOR 

-IOW 

113

+3VS 

VDD[0:3] 

P19 

U511 

LPC 

Super I/O 

PC87393 



C657 

0.1µ 

Error message of keyboard or touch-pad failure is shown or any key does not work. 

-ROMCS 

72 8 

-MCCS 

73 14 

93 

87 

86 

83 

82 

C660 

0.1µ 

C663 

0.1µ 

C658 

0.1µ 

U518 

Level Shift 

SA2 

IRQ1 

IRQ12 

-IOR 

-IOW 

9 

15 

C693 

0.1µ 

-H8_KBCS 

-H8_MCCS 

C692 

0.1µ 

R680 

10K 

+5VA 

C689 

0.1µ 

R681 

10K 

R240 

0 

93 

53 

54 

96 

97 

95 

98 

+5VA 

9,59,4 

VCC1,2,B 

L521 

120Z/100M 

P20 

U517 

Micro 

Controller 

H8/F3437 

H8_VDD5 

37,36 

AVCC 

AVREF 

3 

2 

57 

10 

R656 

1M 

C698 

0.1µ 

KI [0:7] 

KO [0:15] 

T_DATA 

T_CLK 

X503 

16MHZ 

C699 

0.1µ 

+5V 

C683 

68P 

C680 

68P 

RP23 

4.7K*4 

L512 

120Z/100M 

L511 

120Z/100M 

RP21 

47K*8 

MiTac Secret 


+5V 

+5V 

C133 

47P 

L513 

120Z/100M 

C132 

47P 

C131 

0.1µ 

17~24 

1~16 

1 

2 

3 

4 

J15 

Internal Keyboard Connector 

J23 

P19 

P20 

Touch-pad 

114

8.7 Hard Drive Test Error 

Hard Driver Test 

Error 

1. Check if BIOS setup is OK?. 

2. Try another working drive and cable. 

Re-boot 

OK? 

No 

Yes 

Check the system driver for proper 

installation. 

Re - Test 

OK? 

No 

Yes 


Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing 

data to hard disk. 

Replace the faulty parts. 

End 

Board-level 


Replace 

Motherboard 

One of the following parts or signals on the motherboard may 

be defective, use an oscilloscope to check the signals or replace 

the parts one at a time and test after each replacement. 


U508 

R19 

R4 

JS2 

MiTac Secret 


+5VS 

-HDD_RST 

PIORDY 

PDD[0:15] 

PDA[0:2] 

-PDCS3 

-PDCS1 

-PDIOR 

-PDIOW 

-PDDACK 

PDDREQ 

IRQ14 

115

8.7 Hard Drive Test Error 

P13 

U508 

I/O 

Controller 

Hub 

82801CAM 

PDD[0:15] 

PIORDY 

PDA[0:2] 

-PCS1, -PCS3 

-PDIOR 

-PDIOW 

-PDACK 

PDDEQ 

IRQ14 


Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing 

data to hard disk. 

-HDD_RST 

R19 

33 

+5VS 

+5VS 

MiTac Secret 


JS2 

C48 

0.1µ 

R4 

470 

C42 

0.1µ 

D4 

CL-190G 

-BRSTDRV1 

C536 

4.7µ 

-HDDACTP 

D5 

EC10QS04 

39 

41, 42 

3~18 

1 

27 

33,35,36 

37,38 

25 

23 

29 

21 

31 

J7 

P14 

Primary EDIE Connector 

116

8.8 CD-ROM Drive Test Error 


An error message is shown when reading data from CD-ROM drive. 

CD-ROM Driver 

Test Error 

1. Try another known good compact disk. 

2. Check install for correctly. 

Test 

OK? 

No 

Yes 

Check the CD-ROM drive for proper 

installation. 

Re - Test 

OK? 

No 

Yes 

Replace the faulty parts. 

End 

Board-level 


Replace 

Motherboard 





U508 

U517 

U505 

J5 

J506 

X2 

R192 

R667 

M/B 

J1 

SW502 

SW503 

SW504 

SW505 

SW506 

MiTac Secret 


Audio DJ Board 

+5VA 

+5V_CD 

SDD[0:15] 

SDA[0:2] 

-SCS[1,3] 

-SDIOW 

-SDIOR 

-SDACK 

-CDROM_RST 

SIORDY 

IRQ15 

SDREQ 

-PCI_INTE 

117

P13 

U508 

I/O 

Controller 

Hub 

82801CAM 

8.8 CD-ROM Drive Test Error 

Mode 

PAV_EN ISCDROM PCSYSTEM_OFF 

CDPlayer(System off) 1 1 

1 

Direct(system on) 

x x 

0 

Pass through(system on) x x 

0 

no CD-ROM 

1 0 

1 

Power_off 

0 x 

1 

P20 

U517 

Micro 

Controller 

99 

16 


An error message is shown when reading data from CD-ROM drive. 

+3VS 

SDD[0:15] 

SDA[0:2] 

-SCS[1,3] 

-SDIOW 

-SDIOR 

-SDACK 

-CDROM_RST 

SIORDY 

IRQ15 

SDREQ 

-PCI_INTE 

RP572 

47K*8 

BAT_CLK 

BAT_DATA 

+5VA 

R104 

4.7K 

R574 

10K 

+3VS 

R110 0 

R728~R731 

5.6K 

+5V_CD 

R106 

10K 

+5V_CD 

Q5 

DTC144WK 

R572 

47K 

R805 0 

R806 0 

R99 

47K ISCDROM 80 

PCSYSTEM_OFF 

R107 

47K 

L532 

120Z/100M 

ADJ_CLK 

ADJ_DATA 

20 -CONN_STOPEJECT 

21 -CONN_FF 

49 -CONN_RW 

H8/F3437 

31 

11 

-CONN_PLAYPUSE 

R667 1K -ADJ_BTN 

29 

28 

68,70,66 

63,61 

6 

99 

88 

24 

93 

74 

12 

25 

9,58,44 

PWR_CTL 51 

27 

26 

PAV_EN 

U505 

Audio DJ 

VCC[0:2] 

P18 

OZ165 

30 

69,71,67 

64,62 

5 

100 

89 

23 

94 

75 

13 

31 

X2 

8MHZ 

32 

37 

35 

34 

36 

-OZ_RST 

CSDD[0:15] 

CSDA[0:2] 

-CSCS[1,3] 

-CSDIOW 

-CSDIOR 

-CSDACK 

-CCDROM_RST 

CSIORDY 

CIRQ15 

CSDREQ 

3 

2 

4 

1 

+5V_CD 

C112 

2.2µ 

R103 

47k 

C115 

18P 

R592 

C109 

1M 

18P 

+5V_CD 

R519 

4.7K 

+5V_CD 

MiTac Secret 


R520 

10K 

J506 

P18 

8 

10 

9 

11 

3 

JS1 

R192 33 

J1 

8 

10 

9 

11 

3 

C51 

4.7µ 

C45 

0.1µ 

CDROMPWR 

C46 

0.1µ 

-BRSTDRV2 


-CONN_STOPEJECT 

-CONN_FF 

-CONN_RW 

-CONN_PLAYPUSE 

-ADJ_BTN 

38,40,42 

D4 

EC10QS04 

33,33,34 

35,36 

25 

24 

28 

5 

27 

29 

22 

SW502 

SW505 

SW504 

SW503 

SW506 

J5 

P14 

Secondary EDIE Connector 

118



When a print command is issued, printer prints nothing or garbage. 

PIO Port Test Error 

1. Check if PIO device is installed 

properly. (J10) 

2. Check CMOS LPT port setting properly. 

Test 

OK? 

No 

Try another known good 

PIO device. 

No 

Re - Test 

OK? 

No 

Yes 

Yes 

Yes 

Correct it 

Replace the 

faulty parts. 

End 

Board-level 


Replace 

Motherboard 





U511 

U506 

U507 

J10 

RP531 

RP535 

R782 

RP532 

RP536 

MiTac Secret 


+5VS 

P_LPD0 

P_LPD1 

P_LPD2 

P_LPD3 

P_LPD4 

P_LPD5 

P_LPD6 

P_LPD7 

-P_STB 

-P_AFD 

-P_ERR 

-P_INIT 

-P_SLIN 

-P_ACK 

P_BUSY 

P_PE 

P_SLCT 

119


-P_STB 

-P_AFD 

P_LPD0 

-P_ERR 

P_LPD1 

-P_INIT 

P_LPD2 

-P_SLIN 

P_LPD3 

P_LPD4 

P_LPD5 

P_LPD6 

P_LPD7 

-P_ACK 

P_BUSY 

P_PE 

P_SLCT 


When a print command is issued, printer prints nothing or garbage. 

P19 

U511 

LPC 

Super I/O 

PC87393 

54 

53 

52 

51 

50 

49 

48 

47 

46 

45 

44 

43 

42 

41 

40 

37 

36 

RP535 

0*4 

4 

3 

2 

1 

4 

3 

2 

1 

4 

3 

2 

1 

4 

3 

2 

1 

RP531 

0*4 

R782 

0 

RP532 

0*4 

RP536 

0*4 

5 

6 

7 

8 

5 

6 

7 

8 

5 

6 

7 

8 

5 

6 

7 

8 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

12 

11 

10 

9 

8 

7 

6 

5 

U506 

PAC128401Q 

U507 

PAC128401Q 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

13 

14 

15 

16 

17 

18 

19 

20 

4 

21 

3 

22 

X X 

2 

23 

1 

24 

+5VS 

D503 

BAS32L 

MiTac Secret 


GND_IO2 GND_IO2 

STB# 

AFD# 

LPD0 

ERR# 

LPD1 

INIT# 

LPD2 

SLIN# 

LPD3 

LPD4 

LPD5 

LPD6 

LPD7 

ACK# 

BUSY 

PE 

SLCT 

GND_IO2 

1 

14 

2 

15 

3 

16 

4 

17 

5 

18-27 

6 

7 

8 

9 

10 

11 

12 

13 

J10 

P27 

Parallel Port Connector 

120

8.10 USB Test Error 

USB Test Error 

Check if the USB device is installed 

properly. (Including charge board.) 


An error occurs when a USB I/O device is installed. 

Test 

OK? 

No 

Re-test 

OK? 

No 

Yes 

Replace another known good charge 

board or good USB device. 

Yes 

Correct it 

Correct it 

Board-level 


Replace 

Motherboard 

Check the following parts for cold solder or one of the following 

parts on the mother-board may be defective, use an oscilloscope 

to check the following signal or replace the parts one at a time 

and test after each replacement. 

Parts: 

U508 

U18 

U522 

J17 

L527 

L540 

L538 

L526 

L543 

L541 

X5 

MiTac Secret 


Signals: 

25V_USB 

3V_USB 

+5V 

-USBOC0 

-USBOC2 

USBP0+ 

USBP0- 

USBP2+ 

USBP2- 

121

VDD_MEM2.5 

P13 

U508 

I/O 

Controller 

Hub 

82801CAM 

8.10 USB Test Error 

C206 

0.1µ 

+12VS 

+3VS 

R183 

1K 

G 

S D 

Q10 

NDS351AN 

C284 

0.1µ 

25V_USB 

+12VS 

R234 

1K 

G 

S D 

Q11 

NDS351AN 

L32 

120Z/100M 

3V_USB 

L12 

120Z/100M 


An error occurs when a USB I/O device is installed. 

AD[0:31] 

-CBE[0:3] 

-FRAME 

-IRDY 

-TRDY 

-DEVSEL 

-STOP 

PAR 

-PME 

-PCIRST 

-PCI_GNT3 

-PCI_REQ3 

-PCI_INTA 

-PCI_INTB 

-PCI_INTC 

-USB_SMI 

AD21 

L31 

120Z/100M 

VCCPLLA 89 

4,35,53,115 

6 

41,28,19,3 

20 

21 

22 

23 

24 

27 

67 

111 

112 

113 

105 

106 

107 

64 

VCC25_[0:3] 

VCC33_[0:9] 

IDSEL 

P21 

U18 

USB2.0 

Hub 

VT6202 

68 

78 

77 

71 

-USBOC2 

USBP2+ 

USBP2- 

-USBOC0 

USBP0+ 

USBP0- 

+5V 

X5 

24MHZ 

C766 

1µ 

3 

2 

1 

3,4 

4 

VIN0,1 

VOUT1 VOUT0 

5 

C273 

20P 

C281 

20P 

U522 

MiTac Secret 


86 

85 

95 

94 

R208 

1M 

P27 

GND_USB 

1 

C776 

1000P 

R511 

15K 

C777 

1000P 

R27 

15K 

R794 

33K 

R795 

47K 

R512 

15K 

R796 

33K 

R797 

47K 

R28 

15K 

GND_USB GND_USB 

C311 

150µ 

C312 

150µ 

L527 

120Z/100M 

L540 

120Z/100M 

L538 

120Z/100M 

L526 

120Z/100M 

L543 

120Z/100M 

L541 

120Z/100M 

R196 

R756 

C706 

0.1µ 

C705 

0.1µ 

0 

0 

GND_USB 

J17 

P27 

USB Port Connector 

122

8.11 Audio Failure 

Audio Failure 

1. Check if speaker cables are connected 

properly. 

2. Make sure all the drivers are installed 

properly. 

Test 

OK? 

1.Try another known good speaker, 

CD-ROM. 

2. Exchange another known good 

charger board. 

Re-test 

OK? 


No sound from speaker after audio driver is installed. 

No 

No 

Yes 

Yes 

Correct it. 

Correct it. 

Board-level 


Replace 

Motherboard 

Check the following parts for cold solder or one of the following parts on the 

motherboard may be defective,use an oscilloscope to check the following signal 

or replace parts one at a time and test after each replacement. 

1.If no sound cause 

of line out, check 

the following 

parts & signals: 

Parts: 

U14 

U521 

J506 

M/B 

J1 

L10 

L6 

L5 

J503 


Signals: 

AOUT_R 

AOUT_L 

-DEVICE_DECT 

SPDIFOUT 

+3VS 

5V_AMP 

+3VS_SPD 

SPK_OFF 

2. If no sound cause 

of MIC, check 

the following 


Parts: 

U14 

U11 

J505 

J506 

MiTac Secret 


M/B 

J1 

L1 

J501 

Signals: 

MIC 

MIC_2 

MIC_3 

3. If no sound cause 

of CD-ROM, check 

the following 


Parts: 

U14 

R658 

R665 

R661 

J5 

Signals: 

CDROM_LEFT 

CDROM_RIGHT 

CDROM_COMM 

123

+12VS 

C248 

1µ 

P15 

P13 

U508 

I/O 

Controller 

Hub 

82801CAM 

U17 

PCI1410GHK 

8.11 Audio Failure – Audio IN 

U12 

ADP3301AR 

8,7,5 IN0,1 

SD 

P17 

NR 

3 

6 

ERR OUT0,1 

1,2 

R152 330K 

SBSPKR 

R156 

10K 

-CARDSPK 



R189 

10K 

C90 

0.01µ 

-ACRST 

ACSDIN 

ACSYNC 

ACSDOUT 

ACBITCLK 

+3VS 

Q523 

DTC144TKA 

1 

2 

R145 

10K 

AVDDAD 

5 

3 

G 

D S 

Q13 

SI2304DS 

SPK_OFF MUTE_IN 

J507 

MINIPCI 

C283 

0.1µ 

4 

U20 

+5V_CD 

S 

D 

R187 

R613 

R614 

R186 

AVDDAD 

R153 

10K 

G+12VS 

Q3 

SI2304DS 

L9 

102Z/100M 

C677 

10µ 

R695 

0 

R36 

10K 

To next page 

R154 

47K 

Q4 

MMBT3904L 

C242 

0.1µ 

22 

22 

22 

22 

C91 

0.1µ 

+12VS 

AVDDAD 

R769 

47K 

C264 

0.1µ 

MINIPCI_SPKR 

25,38 

11 

8 

10 

C768 

0.1µ 

5 

6 

12 

+3VS 

L519 

102Z/100M 

C278 

0.1µ 

AVDD1,2 

U14 

Audio Codec 

PC_BEEP 

P17 

C695 

0.1µ 

ALC202 

1,9 

DVDD1,2 

21 

23 

24 

20 

18 

19 

2 

3 

C257 

1µ 

C239 

0.1µ 

AVDDAD 

C288 

22P 

X6 

24.576MHZ 

C289 

22P 

8 

MIC 7 

C246 2.2µ 

C676 1µ 

C266 1µ 

C260 1µ 

R155 

47K 

VCC+ 1OUT 

U11 

MC33078D 

2OUT 

C227 220P 

R164 22K 

C682 

100P 

C686 

100P 

R659 

100K 

1IN+ 

1IN- 

2IN+ 

2IN- 

1 

3 

2 

5 

6 

R654 

100K 

R666 

100K 

R168 

47K 

C220 10µ 

R517 

4.7K 

R513 

6.8K 

R657 

100K 

R662 

100K 

213 

10µ 

R658 1K 

R665 1K 

R661 1K 

R173 

68K 

R171 

100K 

R174 

2.7K 

C509 

0.068µ 

R650 1K LINE_IN_L 

R653 1K 

LINE_IN_R 

1 

2 

J505 

MIC 

MIC_3 15 

MIC_2 14 

SPDIFOUT 

48 18 

35 

36 

C247 2.2µ 

AOUT_L 

AOUT_R 

To next page 

MiTac Secret 


L26 

L27 

CDROM_RIGHT 

CDROM_LEFT 

CDROM_COMM 

120Z/100M 

120Z/100M 

AGND 

Internal 

Microphone 

17 

16 

2 

1 

3 

J506 

P18 

J5 

P14 

CDROM 

Connector 

124

+5V_CD +5V_AMP 

D507 

EC10QS04 

C779 

0.1µ 

+5VA 

MUTE_IN 

From previous page 

AOUT_L 

AOUT_R 

From previous page 

8.11 Audio Failure – Audio OUT 

C780 

0.1µ 

+5V_AMP 

C731 0.47µ 

C118 

100µ 

D506 

BAT54C 

2 

1 

+5V_AMP R162 

100K 



3 

C113 

0.47µ 

18,3,8 

C742 

0.47µ 

C726 

0.47µ 

9 

MUTE_IN 2 

C732 0.47µ C739 39K 20 

C727 39K 

16 

C746 0.47µ 19 

C733 0.47µ 17 

R779 0 14 

VDD 

PVDD0,1 

VAUX 

P17 

U521 

SHUTDOWN# 

Amplifier 

TPA0252 

LLINE IN 

RLINE IN 

LHP IN 

RHP IN 

HP/LINE# 

SE/BTL# 

HP/LINE# 

13 

11 

23 

1 

22 

14 

4 

5 

SPKROUT+ 

SPKROUT- 

SPKLOUT+ 

SPKLOUT- 

R779 

0 

C781 

0.1µ 

C94 

220µ 

R160 

1K 

SE/-BTL 

Low 

High 

C108 

220µ 

R717 

1K 

HP/-LINE 

SW501 

SW507 

Low 

High 

1 

2 

1 

2 

R723 

100K 

R 

L 

Q513 

DTC144TKA 

-DEVICE_DECT 

High 

Low 

J508 

Internal Speaker Connector 

J501 

5V_AMP 

R1 

100K 

R2 

100K 

Input 

L/R Line 

L/R HP 

R722 

47K 

R1 

Output 

BTL 

SE 

-DEVICE_DECT 

LINE_OUT_L 

LINE_OUT_R 

-VOL_UP 

-VOL_DN 

+5V_CD 

-VOL_UP 

-VOL_DN 

J506 

+3VS 

-DEVICE_DECT 

LINE_OUT_L 

LINE_OUT_R 

SPDIFOUT 

+3VS 

R508 

0 

R507 

10K 

Q502 

DTC144TKA 

+5V_CD 

MiTac Secret 


P18 

6 

5 

6 

5 

J1 

21 

20 

19 

18 

17 

16 

15 

14 

LINE_IN_L 

LINE_IN_R 

MIC_3 

MIC_2 

L6 

600Z/100M 

L5 

600Z/100M 

L11 

600Z/100M 

L3 

600Z/100M 

L2 

600Z/100M 

Q501 

SI2301DS 

S D 

G 

R1 

R501 

4.7K 

+3VS_SPD 

-DECT_HP/OPT 

L10 

600Z/100M 

L9 

600Z/100M 

L12 

600Z/100M 

L7 

600Z/100M 

L4 

600Z/100M 

5 

4 

2 

3 

1 

8 

7 

9 

L8 

600Z/100M 

R506 

4.7K 

L1 

1 

600Z/100M L16 

600Z/100M 

CAGND 


+5VS 

J503 

LINE OUT 

Drive 

1 

2 

4 

5 

3 

CAGND 

3 

4 

5 

2 

IC 

LED 

J502 

J501 

125


LAN Test Error 

Test 

OK? 

An error occurs when a LAN device is installed. 

1.Check if the driver is installed properly. 

2.Check if the notebook connect with the 

LAN properly. 

No 

Check if BIOS setup is ok. 

Re-test 

OK? 

No 

Yes 

Yes 

Correct it. 

Correct it. 


Board-level 


Replace 

Motherboard 



to check the following signal or replace the parts one at a time and 

test after each replacement. 


508 

U6 

U512 

U501 

U7 

J12 

R127 

R74 

R144 

R29 

R71 

R619 

R624 

R502 

R501 

MiTac Secret 


+3V 

+3V_LAN 

AVDD_LAN 

-PCIRST 

-PCIRST_MSK 

-PCIRST_N 

TXD+ 

TXD- 

RXIN+ 

RXIN- 

126

127 



N/B Maintenance 


An error occurs when a LAN device is installed. 

U7 

PH163112 

TXD+ 

TXD- 

C195 

22P 

7 

2 

3 

P16 

PJRX+ 

PJTX+ 

PJRX- 

PJTX- 

11 

9 

16 

14 

15 

10 

R619 

75 

R502 

75 

R624 

75 

R501 

75 

C574 

1000P 

PJ7 

PJ4 

1,2 

4,5 

6 

3 

8 

7 

P16 

J12 

92 

91 

R139 

51 

R141 

51 

C207 

0.1µ 

3 

2 

4 

1 

C662 

10P 

C661 

10P 

X502 

25MHZ 

78 

79 

1 

RJ45 LAN Connector 

L518 

120Z/100M 

+3V +3V_LAN 

C176 

C181 

C182 

0.1µ 

C177 

4.7µ 

C165 

C166 

C167 

0.1µ 

C670 

C671 

2.2µ 

GND_45 

JS504 

U6 

LAN 

Controller 

RTL8139CL 

P16 

U508 

I/O 

Controller 

Hub 

82801CAM 

P13 

IDSEL 

AD18 

-CBE[0:3] 

R127 

100 

AD[0:31] 

-FRAME 

-IRDY 

-TRDY 

-DEVSEL 

-STOP 

-PERR 

-SERR 

-PME 

PAR 

-PCI_GNT2 

-PCI_REQ2 

-PCI_INTD 

+3V_ICH 

-PCIRST_MSK 

-PCIRST 

1 

2 

R629 

4.7K 

R138 

10K 

Q7 

DTC144TKA 

+3V 

-PCIRST_N 

A 

B VCC 

Y 

5 

4 

U512 

NC7S32 

-PCLKRUN 

3 

15 

16 

17 

19 

20 

21 

22 

76 

75 

23 

117 

118 

114 

L23 

120Z/100M 

AVDD_LAN 

R132 

51 

R136 

51 

C197 

22P 

R128 

0 

AVDD_LAN 

C192 

0.1µ 

R74 

0 

R144 

0 

R29 

0 

R71 

0 

8 

6 

C208 

0.1µ 

RXIN+ 

RXIN- 

87 

86 

R121 

0 

115 

+3VS 

CS 

SK 

DI 

DO 

50 

49 

48 

47 

1 

2 

3 

4 

VCC 

GND 

8 

5 

C223 

0.1µ 

+3V_LAN 

U501 

9346A 

R125 

15K 

R122 

1K 

95 

ISOLATE# 

+3V R150 

5.6K 

61 

+3V_LAN 

VDD[0:6] 

VDD[12:14] 

RST# 

AVDD_LAN 

L22 

120Z/100M 

VDD[9:11] 

L_AGND 

L_AGND 

L_AGND 

GND_45 

L24 

120Z/100M 

L_AGND 

L21 

120Z/100M 

AVDD_LAN 

L_AGND 

MiTac Secret 


PC Card Socket and 

IEEE1394 Failure 

1. Check if the PC CARD or 1394 device 

is installed properly. 

2. Confirm PC card or 1394 driver is 

installed ok. 

Test 

OK? 

No 

Re-test 

OK? 

No 

Yes 

Try another known good PC card or 

1394 device. 

Yes 

Correct it 



An error occurs when a PC card device or 1394 device is installed. 

Change the faulty 

part then end. 

Board-level 


Replace 

Motherboard 



to check the following signal or replace the parts one at a time and 

test after each replacement. 

Parts: 

U508 

U17 

U512 

U13 

U10 

U503 

U15 

J13 

J16 

Q12 

Q9 

X504 

R238 

R239 

R788 

R789 

MiTac Secret 


Signals 

-VCCEN0 

-VCCEN1 

SDATA 

SCLK 

-VPPEN0 

VPEEN1 

-CIRDY 

-CPERR 

-CSERR 

-CSTOP 

-CTRDY 

CCD[1,2] 

CAD[0:31] 

-CCBE[0:3] 

-CINT 

-CREQ 

-CRST 

-CGNT 

-CAUDIO 

-CBLOCK 

-CCLKRUN 

-CDEVSEL 

R2_D2 

R2_D14 

R2_A16 

CCLK 

CPAR 

CVS[1,2] 

CSTCHG 

PHY_D[0:7] 

PHY_CTL[0,1] 

PHY_LREQ 

PHY_CLK 

PHY_LKON 

TPA+ 

TPA- 

TPB+ 

TPB- 

128

+3V_ICH 

-PCIRST_MSK 

R138 

10K 

P13 

U508 

R629 

4.7K 

Q7 

DTC144TKA 

I/O 

Controller 

Hub 

82801CAM 

+3V 



2 

-PCIRST 

An error occurs when a PC card device or 1394 device is installed. 

U512 

NC7S32 

1 

B VCC 

A 

R157 

10K 

AD[0:31] 

-CBE[0:3] 

-FRAME 

-IRDY 

-TRDY 

-DEVSEL 

-STOP 

-PERR 

-SERR 

-PME 

-PCLKRUN 

PAR 

-SUSB 

-PCI_GNT1 

-PCI_REQ1 

-PCI_INTA 

-PCI_INTC 

5 

+3V 

4 -PCIRST_N 1 

5 

Y 

B VCC 

+3V_ICH 

-GATE1394 2 4 -CBRST 

A Y 

R181 

10K 

AD19 

-1394WR 

R179 

100 

U13 

NC7S08 

IDSEL 

P15 

U17 

PCMCIA/ 

IEEE1394 

Controller 

PCI4410GHK 

-1394WR 

PHY_D [0:7] 

-VCCEN0 

-VCCEN1 

SDATA 

SCLK 

-VCCEN1 

-VCCEN0 

VPPEN0 

VPPEN1 

PHY_CTL[0,1] 

PHY_LREQ 

PHY_CLK 

PHY_LKON 

L514 

120Z/100M 

Q12 

DTC144WK 

Q9 

DTC144WK 

To J13 

+3V 1394AVDD 

R647 10 

R634 1K 

+12V 

R633 

10K 

+3V 

9 

2 

1 

15 

14 

6-13 

4,5 

1 

2 

19 

20-22 

14 

R172 

47K 

R163 

47K 

VCCD1 

VCCD0 

VDDP0 

VDDP1 

PC [0:2] 

PD 

R177 

4.7K 

AVDD [0:4] 

U503 

R176 

4.7K 

U10 

DVDD [0:3], PLLVDD 

TPBAIS 

TSB41AB1 

+3V 

TPS2211A 

P15 

P15 

37 

36 

34 

35 

38 

59 

60 

+5V 

3.3VA,B 

5VA,B 

AVCCC,B,A 

AVPP 

PHY_XI 

PHY_XO 

C263 

0.1µ 

Write Protect 

when high 

3,4 

5,6 

11-13 

10 

TPA+ 

TPA- 

TPB- 

TPB+ 

C236 

0.1µ 

8 

7 

C687 

10P 

X504 

24.576MHZ 

C688 

10P 

VCC 

WC- 

5 

SDA 

6 

SCLK 

MiTac Secret 


C244 

0.1µ 

U15 

NM24C02N 

+3V 

P15 

C228 

0.1µ 

R643 

56 

C229 

0.1µ 

+5V 

R645 

56 

C679 

1µ 

-CIRDY 

-CPERR 

-CSERR 

-CSTOP 

-CTRDY 

-CCD 1,2 

CAD [0:31] 

-CCBE [0:3] 

R24 

56 

R663 

4.99k 

VCCA VPPA 

C221 

0.1µ 

-CINT 

-CREQ 

-CRST 

-CGNT 

-CAUDIO 

-CBLOCK 

-CCLKRUN 

-CDEVSEL 

C201 

0.1µ 

R26 

56 

C668 

270P 

C232 

0.1µ 

R789 0 

R788 0 

R238 0 

R239 0 

1394_GND 

R2_D2 

R2_D14 

R2_A16 

CCLK 

CPAR 

CVS[1,2] 

CSTCHG 

C202 

0.1µ 

JS503 

SHORT_SMT4 

4 

3 

1 

2 

GND1,2 

J13 

P15 

Card Bus Socket 

J16 

P15 

IEEE1394/4P 

129

9. Spare Parts List - 1 

Part Number Description Location(S) 

442671200007 AC ADPT ASSY;19V/4.74A,8170,LITE 

361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA 

361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W) 

541667310001 AK;01-EN,BOX,8060 

541667310032 AK;EN,8060,UTILITY ONLY 

346673100044 AL-FOIL;2FAN,MB,8060 

346673100045 AL-FOIL;BATTERY,MB,8060 

346673100043 AL-FOIL;PIO,MB,8060 

422673100032 ANTENNA;LCD R,8060 

441504100001 BATT ASSY;LI,9CELLS/6AH,8060 

442673100003 BATT,ASSY;11.1V/6AH,LI-PANASONIC 

338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA 

340673100027 BEZEL ASSY;SLOT COMBO,MKE,8060 

291000013019 BFM-SC,CON;HDR,FM,15P*2,1MM,ST,7 J8 

291000810812 BFM-SC,CON;PHONE JACK,8P,R/A,RJ4 J12 

291000410204 BFM-SC,CON;WFR,MA,2P,1.25,ST,SMT J501,J503,J505,J508,J509 

242670800113 BFM-WORLD MARK;WINXP,7521N 

221673140001 BOX;AK,8060 

340673100004 BRACKET ASSY;TP,8060 

342670500012 BRACKET;CD-ROM,TETRA 

342673100006 BRACKET;LCD LEFT,8060 

342673100007 BRACKET;LCD RIGHT,8060 

421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C 

421673400005 CABLE ASSY;TV-OUT,8640S 

272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT C3,C16 



MiTac Secret 


272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT C20,C21,C22 

272075103702 CAP;.01U ,50V,+80-20%,0603,SMT C161,C270,C294,C296,C298,C299 

272075103702 CAP;.01U ,50V,+80-20%,0603,SMT PC16,PC524 

272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S C506,C549,C562,C565,C570,C573 

272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S PC14,PC521 

272072473402 CAP;.047U,16V ,10%,0603,X7R,SMT C307,C65,C741,C86 

272072473401 CAP;.047U,16V ,10%,0603,X7R,SMT C7 

272073104703 CAP;.1U ,25V,+80-20%,0603,X7R,S C1,C4,C8 

272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C10,C100,C101,C102,C103,C104,C 

272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C502,C503,C504,PC11,PC20,PC25 

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S C24,C26,C4,C6 

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S C3,C5 

272003104701 CAP;.1U ,CR,25V ,+80-20%,0805,Y PC17,PC2,PC22,PC8 

272072334701 CAP;.33U ,CR,16V ,+80-20%,0603,Y C9 

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S C113,C726,C730,C731,C732,C733 

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S C23,C28 

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S C1 

272002474401 CAP;.47U ,CR,16V ,10%,0805,X7R,S C13,C14 

272003683401 CAP;0.068U,CR,25V,10%,0805,X7R C509 

272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C135,C137,C225,C233,C32,C33,C5 

272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S PC10,PC13,PC18,PC21,PC24,PC5 

627207510241 CAP;1000P,50V ,10%,0603,X7R,SMT C25 

272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C14,C3,C574 

272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C110,C114,C116,C43,C49,C50,C6 

272431105901 CAP;100U ,10V ,20%,7343,SMT C118 

130



272431107510 CAP;100U,2V,20%,7343,SP-CAP PC4,PC5 

272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C661,C662,C687,C688 

272011106703 CAP;10U ,10V,+80-20%,1206,Y5V,1 PC1,PC12,PC23,PC3 

272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S PC21,PC553,PC75,PC76,PC9 

272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S PC501,PC502,PC515 

272043106401 CAP;10U,25V,+-10%,1812,X5R,SMT,T PC32,PC43,PC44,PC525,PC526,P 

272993106001 CAP;10U,25V,2.2mm,X5R,KYOCERA,SM PC47,PC61 

272011106404 CAP;10U,6.3V,10%,1206,X7R,SMT C13,C15,C16,C2,C213,C220,C23,C 

272075120301 CAP;12P ,CR,50V ,5% ,0603,NPO,S C172,C173 

272431227503 CAP;150U ,POLY,6.3V,20%,7243,SMT C214,C311,C312 

272433156502 CAP;15U ,TQC,25V,20%,H=1.9 ,7343 PC42,PC506,PC507,PC58 

272433156502 CAP;15U ,TQC,25V,20%,H=1.9 ,7343 PC15,PC19 

272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S C109,C115,C47,C56 

272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C191,C196,C224,C226,C241,C248 

272002105403 CAP;1U ,CR,16V,10%,0805,X7R,SM C6 

272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, C18,C4,PC49,PC50,PC515,PC73,P 

272001225401 CAP;2.2U ,CR,10V ,10%,0805,X5R,S C5 

272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C119,C130,C246,C247,C96,C99,PC 

272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C112,C301,C670,C671,C783 

272075200302 CAP;20P ,CR,50V ,5% ,0603,SMT C273,C281 

272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C508,C575,C578,C581 

272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT C1,C17,C20,C227,C669 

272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT PC27,PC523 

272431227001 CAP;220U, 2.5V,TPE, 7343,18MR PC514,PC519 

272421225501 CAP;220U,TPE,4V,20%,7343,SMT PC23,PC38,PC39 



MiTac Secret 


272421225501 CAP;220U,TPE,4V,20%,7343,SMT PC30,PC31 

272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S C11 

272075220303 CAP;22P ,50V ,5% ,0603,NPO,SMT C111,C117,C195,C197,C288,C289 

272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S C11,C519,C520,C521 

272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C200,C204,C216,C217,C668,C755 

272075209001 CAP;2P ,CR,50V ,+-0.25PF,0603, C13 

272075331701 CAP;330P ,50V, +/-20%,0603,X7R,S PC516 

272431337506 CAP;330U,4V,20%,7343,SMT PC517 

272075330401 CAP;33P ,CR,50V ,10%,0603,X7R,S C209,C212,C215 

272421336501 CAP;33U,TT,8V,20%,3528,SMT C22,C25,C545,C546 

272002475701 CAP;4.7U ,CR,10V ,+80-20%,0805,S C168,C169,C171,C178,C186,C267 

272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C177,C51,C536,PC27,PC37,PC519 

272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y PC507,PC511PC507,PC511 

272012475502 CAP;4.7U ,CR,16V,20%,1206,Y5U,SM C14 

272013475701 CAP;4.7U ,CR,25V ,+80-20%,1206,S C2 

272075472701 CAP;4700P,50V ,+ -20%,0603,X7R,S C55,C554,C555,C557,C560,C563,C 

272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C57,C571,C59,C60,C602,C603,C60 

272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC5 

272072471301 CAP;470P ,CR,16V ,5% ,0603,NPO,P C12 

272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,S C132,C133,C185,C189,PC16 

272431476502 CAP;47U ,6.3V,20%,SP-CON,7343,S PC28,PC46,PC51,PC57 

272431476502 CAP;47U ,6.3V,20%,SP-CON,7343,S C2 

272030680402 CAP;68P ,3KV,10%,1808,NPO,SMT,P C15 

272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C680,C683 

221673150002 CARD BOARD;FRAME,PALLET,8060 

131



221673150003 CARD BOARD;TOP/BTM,PALLET,8060 

221600020128 CARTON;380MM*320MM*320MM,BC FLUT 

221503220001 CARTON;BATTERY,GRAMPUS 

221673120003 CARTON;N-B,8060 

431673100001 CASE KIT;8060 

335152000044 CFM-BAT;FUSE THERMAL 98'C 

342665500008 CFM-SUYIN;S-STANDOFF,#4-40H4.8,N 

273000500052 CHOKE COIL;0.7UH,1.6mOHM,25%,20A PL1,PL2 

273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L13,L25,L28,L535 

273000500015 CHOKE COIL;50UH(REF),D.4*2,5.5T, L1 

273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L539,L542 

523467310018 COMBO ASSY;CW-8121,KME,8060 

331000007021 CON;BAT,7P,2.5mm,SUYIN J18 

291000001001 CON;BATTERY,10P,FM,2MM,R/A,SMT 

331000007016 CON;BATTERY,7P,2.5MM,250132FB007 

331720025012 CON;D,FM,25P,2.77,R/A,TITAN J10 

291000151204 CON;FPC/FFC,12P,.5MM,R/A,SMT,RED J2 

291000142406 CON;FPC/FFC,24P,0.5MM,H=2,R/A,SM J506 

291000142406 CON;FPC/FFC,24P,0.5MM,H=2,R/A,SM J1 

291000142402 CON;FPC/FFC,24P,1MM,H5.5,ST,ACES J15 

291000150411 CON;FPC/FFC,4P,1MM,R/A,SMT,85202 J23 

291000150411 CON;FPC/FFC,4P,1MM,R/A,SMT,85202 J1 

291000012411 CON;HDR,12P*1,1.25,ACES,SMT J2 

291000013021 CON;HDR,FM,15P*2,0.8MM,ST,H=5.2, J20 

291000022608 CON;HDR,FM,18P*2,2.54mm,3A,R/A,S J502 



331040044017 CON;HDR,FM,22P*2,2MM,H=5.4,R/A,D J7 

331040050016 CON;HDR,FM,25P*2,0.8MM,H=2,R/A,D J5 

291000021101 CON;HDR,MA,11P*1,1.25,R/A,DF13-1 J1 

291000013016 CON;HDR,MA,15P*2,1MM,H4.25,ST,SM J4 

291000022607 CON;HDR,MA,18P*2,2.54mm,3A,R/A,S J9 

291000020202 CON;HDR,MA,2P*1,1.25,R/A,SMT,HIR J21 

291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM J2 

291000010301 CON;HDR,MA,3P*1,1.25MM,ST,SMT J22 

291000020304 CON;HDR,MA,3P,1.25MM,H3.5MM,R/A, J2 

291000256821 CON;IC CARD,68P,.635MM,62598-22A J13 

331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A J16 

331870007005 CON;MINI DIN,7P,R/A,W/GROUND,351 J6 

291000000802 CON;MINI PCI SOCKET,0.8MM,H4.0,S J507 

331810006044 CON;PHONE JACK,6P2C,H11.5,RJ11,T J3 

331910002006 CON;POWER JACK,2P,20VDC,5A,DIP J19 

331840010008 CON;STEREO JACK,10P,W/SPDIF,R/A, J503 

331840005007 CON;STEREO JACK,5P,R/A,W9.1,LGY2 J501,J502 

331000008062 CON;USB,FM,H15.54,R/A,4P*2,SUYIN J17 

345673100028 CONDUCTIVE_TAPE;TP,COVER,8060 

342668200003 CONTACT PLATE;2,W4L20T0.15 

342503400004 CONTACT PLATE;W5L45T0.13,7170LI, 

342673100025 CONTACT PLATE;W5L46T0.13 ,2T,806 

342673100024 CONTACT PLATE;W5L62T0.13 ,1/3T,8 

342504300003 CONTACT PLATE;W5L63T0.13,8500 

342673100023 CONTACT PLATE;W5L80T0.13 ,1/5T,4 

MiTac Secret 


132



342503400002 CONTACT PLATE;W5L9T0.13,7170LI,P 

313000150109 CORE;110OHM/100MH,15.0*14.0*23.0 

340673100001 COVER ASSY;8060 

340673100021 COVER ASSY;DDR,8060 

340673100002 COVER ASSY;HINGE,8060 

340673100007 COVER ASSY;LCD,8060 

340673100022 COVER ASSY;MINIPCI,8060 

344673100008 COVER;BATT,8060 

344673100006 COVER;HDD,8060 

272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP502,CP503 

227673100002 CUSHION;FRAME,FDD,AK BOX,8060 

227673100003 CUSHION;TOP/BTM,FDD,AK BOX,8060 

323760000025 DDR SODIMM MODULE;256MB,77.11021 

331660020004 DIMM SOCKET;DDR SODIMM 200P, CA0 J11 

291000612004 DIMM SOCKET;DDR,200P,0.6MM,H4,SM J502 

288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D503,PD19 

288100054001 DIODE;BAT54,30V,200mA,SOT-23 PD3,PD5,PD6 

288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 D506,D6,D9 

288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D505,PD506,PD508 

288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1,D2 

288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1 

288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD18,PD501,PD507,PD7 

288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD2 

288100084002 DIODE;BZX84C5V6,5.2~6V,350mA,SOT ZD1,ZD2 

288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, D4,D5,D507,PD12,PD9 



MiTac Secret 


288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, PD501,PD502 

288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 D502,PD11 

288103103001 DIODE;EC31QS03L,30V,3A,SMT PD1,PD13,PD14,PD15,PD16,PD1 

288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT PD10 

288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D1,D7 

288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD509 

288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM PD505 

288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD5 

288100018003 DIODE;UDZS18B,ZENER,18V,SOD-323, ZD3,ZD4 

523467240008 DVD COMBO DRIVE;CW-8121,MKE 

272601227501 EC;220U ,10V,M,6.3*7.7,-15+105', C108,C94 

312278206152 EC;820U ,4V,+-20%,10X10.5,FPCAP PC1,PC3,PC6,PC8 

227673100001 END CAP;L/R,8060 

227672300004 EPE PAD;K/B,MANGUSTA 

481673100002 F/W ASSY;KBD CTRL,8060 U517 

481673100001 F/W ASSY;SYS/VGA BIOS,8060 U510 

481673100001 F/W ASSY;SYS/VGA BIOS,8060 U510 

340673100023 FAN ASSY;HOUSING,8060 

273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN FA501 

273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN FA1 

273000130019 FERRITE CHIP;120OHM/+-10%/100MHZ L10,L11,L15,L21,L22,L23,L24,L5 

273000130019 FERRITE CHIP;120OHM/+-10%/100MHZ L16,L8 

273000130019 FERRITE CHIP;120OHM/+-10%/100MHZ L501,L502 

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L12,L16,L17,L18,L19,L26,L27,L2 

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L503,L504,PL1,PL2 

133



273000150001 FERRITE CHIP;220OHM/100MHZ,2012, L1 

273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L1,L10,L11,L12,L2,L3,L4,L5,L6,L 

332673100002 FFC;AUDIO,8060 

332673100003 FFC;TP,8060 

332673100004 FFC;TP,MB,8060 

288003602001 FIR;HSDL-3602-007,FRONT VIEW,10P U19 

245600010016 FLOW CARD;SPS,GRAY 

245600010030 FLOW CARD;SPS,PINK,100MM*30MM,PR 

295000010044 FUSE;1.1A/6V,POLY SWITCH,1210,SM F501,F502 

295000010057 FUSE;228R,139C',5A/250V,SMT,PRC 

295000010126 FUSE;FAST,2A,63VDC,1206,SMT,PRC F1 

335152000062 FUSE;LR4-730,POLY SWITCH,PRC 

295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1,PF501,PF502 

345673100027 GASKET;AUDIO,PCB,8060 

345673100024 GASKET;PCMCIA,MB,8060 

230000010004 GLUE;9001B,BLACK,PRC 

230000010003 GULE;9001A,BLACK,PRC 

523401634005 HD DRIVE;40GB,2.5",IC25N040ATCS0 

523467310003 HDD ASSY;40G,IBM IC25N040ATCS04, 

451673100031 HDD ME KIT;8060 

340673100003 HEATSINK ASSY;8060 

342673100021 HEATSINK;MOS,TV-OUT,8060 

342673100020 HEATSINK;NORTH BRIDGE,8060 

342673100026 HEATSINK;VGA,8060 

341673100005 HINGE;LCD LEFT,8060 



341673100004 HINGE;LCD RIGHT,8060 

344673100045 HOLDER;PCMCIA,FCI-54922-22L0C,80 J13 

340673100009 HOUSING ASSY;8060 

340673100008 HOUSING ASSY;LCD,8060 

451673100071 HOUSING KIT;8060 

344673100007 HOUSING;BATT,8060 

291000614793 IC SOCKET;UPGA479M,479P,MOLEX U1 

282574373004 IC;74AHC373,OCT D-TRAN,TSSOP,20P U8 

282574186002 IC;74AHCT1G86,SINGLE,XOR,SOT23,S U20 

282074338402 IC;74CBTD3384,10 BIT BUS SW,TSOP U518 

282574164002 IC;74VHC164,SIPO REGISTER,TSSOP, U501 

284508139005 IC;8139CL,LAN CONTROLLER,LQFP,12 U6 

284501032001 IC;ADM1032,TEMPERATURE MTR,SO8 U502 

286303301001 IC;ADP3301AR-5,.8%,REG.,SO,8P U12,U21 

284500202005 IC;ALC202,AC97 CODEC,LQFP,48P,SM U14 

286308800006 IC;AME8800AEEV,VOL REG.,SOT23-5, PU23 

286308801006 IC;AME8801CEEV,VOL REG.,SOT23-5, PU6 

286308801002 IC;AME8801MEEV,VOL REG.,SOT23-5, PU505 

286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT U3 

284582845009 IC;BROOKDALE-M,82845MP,FC-BGA593 U3 

284508500002 IC;CM8500,3A BUS TERMINATOR,PTSS PU4 

324180786285 IC;CPU,MOBILE P4-NORTHWOOD,2.0G, 

283466570001 IC;EEPROM,9346,64*16 BITS,SO8,SM U501 

283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U15 

283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U2 

MiTac Secret 


134



286305234001 IC;FAN5234,PWM,QSOP,16P PU9 

283450083002 IC;FLASH,512K*8-70,PLCC32,ST39SF 

283450083002 IC;FLASH,512K*8-70,PLCC32,ST39SF 

284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P, U517 

284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P, 

284500003010 IC;ICH3-M,SOUTH BRIDGE,BGA,421P U508 

284595080001 IC;ICS950805,200MHZ,TSSOP56 U5 

286300811002 IC;IMP811,RESET CIRCUIT,4.38,SOT U524 

286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU22 

286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S PU506 

286303707001 IC;LTC3707,PWM SWITCH REG,SOOP,2 PU501 

286303716001 IC;LTC3716,PWM,QSOP,36P PU5 

286301632002 IC;MAX1632CAI,PWM CTRL,SSOP,28P PU507 

286301772001 IC;MAX1772,PWM,QSOP,28P PU21 

286300809002 IC;MAX809S,RESET CIRCUIT,2.9V,SO U509 

286133078001 IC;MC33078D,LOW NOISE OP AMP.,SO U11 

286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR U5 

284500017005 IC;MOBILITY,MAP17- 440(64MB),BGA U4 

281300732001 IC;NC7S32,SINGLE OR GATE,SC70-5 U512 

281307085001 IC;NC7SZ08P5,2-INPUT & GATE,SC70 U13,U523 

284500165001 IC;OZ165,AUDIO DJ,TQFP,100P U505 

286300965001 IC;OZ965R,CCFL CTRL,TSSOP16,O2 U1 

284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSO U506,U507 

284587393002 IC;PC87393F,TQFP,100P U511 

284504410005 IC;PCI4410A,CARDBUS/OHCI,uBGA,20 U17 



286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U522 

286300812002 IC;S-812C,DECECTOR,SOT-89,PRC U1 

286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ17,PQ6 

286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ1 

284500530002 IC;SM530, SPREAD CLOCK,TSSOP20 U504 

286300055001 IC;TC55,3.3V,250mA,REG.,SOT89 PU10 

286100252001 IC;TPA0252,AUDIO AMP,2W,TSSOP,24 U521 

286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U10 

286362003001 IC;TPS62003,LOW POWER,MSOP,10P U2 

284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U515 

284506202001 IC;VT6202L,PCI USB2.0 CTL,PQFP12 U18 

273000114002 INDUCTER;4.7UH,10%,1206,SMT L504,L505 

273000135101 INDUCTOR;10UH,10%,1608,SMT L4 

273000990012 INDUCTOR;10UH,CDRH127,SUMIDA,SMT PL7,PL8 

273000990031 INDUCTOR;10UH,CDRH127B,SUMIDA,SM PT1 

273000990115 INDUCTOR;3.3uH,3A,CSS054D,SMT PL501 

273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 

273000990117 INDUCTOR;4.7UH,CDRH127,MULTI,SMT PL3 

273000990117 INDUCTOR;4.7UH,CDRH127,MULTI,SMT PL502,PL503 

346503100005 INSULATOR;5,BATTERY ASSY,7521Li 

346673100008 INSULATOR;B,BATT,8060 

346503400502 INSULATOR;BATT ASSY,L22R9.2,8175 

346673100025 INSULATOR;BATT ASSY,L91.6W14MID8 

346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL 

346673100026 INSULATOR;BATT ASSY,POLY,W30L52, 

MiTac Secret 


135



346673100027 INSULATOR;BATT ASSY,W13L20,BLAC, 

346503400503 INSULATOR;BATT ASSY,W7L13,8175 

346673100040 INSULATOR;DCJACK,8060 

346673100028 INSULATOR;DDB,CMP,8060 

346673100023 INSULATOR;FOR 4 CELLS ,8060 

346503200003 INSULATOR;FOR 5 CELLS,GRAMPUS 

346669900004 INSULATOR;INVERTER,7170 

346673100039 INSULATOR;MB,8060 

346673100030 INSULATOR;MB,CAPACITOR,8060 

346503900001 INSULATOR;PCB ASSY,W15L52,8575 

346673100014 INSULATOR;TP_PCB,8060 

541150340202 INVERTER BD;STINGRAY (FOR 8640) 

531017240064 KBD;87,KR-26FB-GRWC01,ZIPPY,8060 

451673100092 LABEL KIT;N-B,8060 

242600000145 LABEL;10*10,BLANK,COMMON 



242662300009 LABEL;25*10MM,3020F 

242600000434 LABEL;25*6,HI-TEMP,COMMON 




242673100005 LABEL;AGENCY-GLOBAL,8060 

242600000088 LABEL;BAR CODE,125*65,COMMON 

242673100002 LABEL;BATT,PANA,MSL,LI-ION,8060 



242669900009 LABEL;BLANK,60*80MM,7170 

242664800013 LABEL;CAUTION,INVERT BD,PITCHING 

242669600005 LABEL;LOT NUMBER,RACE 

242600000315 LABEL;RED ARROW HEAD,PRC 

242600000315 LABEL;RED ARROW HEAD,PRC 

441673100031 LCD ASSY;AU,WXGA,15.2",8060 

451673100051 LCD ME KIT;WXGA,15.2",8060 

413000020345 LCD;B152EW01,TFT,15.2",LVDS,WXGA 

294011200158 LED;BLUE,H=1.9,2.8X3.2MM,DDB-11, D1 

294011200155 LED;BLUE,H0.8,SF0603-B70140-30,S D11,D4,D5,D6,D7,D8 

294011200161 LED;BLUE,H1.1,SF0805-B65140-38,S D6 

294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 LED1,2,3,4 

294011200070 LED;RED/GREEN,19-22SRVGC/TR8,LED LED5,6 

416267310001 LT PF;AU,WXGA,15.2",8060 

526267310005 LTXNX;8060/5UGB/40I/1GR1/L2D3A/X 

561567310001 MANUAL KIT;EN,8060,N-B 

561567310013 MANUAL;USER'S,EN,8060,N-B 

375102010002 NUT-HEX;M2X1.5,NIW 

461504100001 PACKING KIT;8060,BATT,LI 

461673100003 PACKING KIT;N-B,8060 

224670830002 PALLET;1250*1080*130,7521N 

221673150001 PARTITION;AK BOX,8060 

221503250001 PARTITION;BATTERY,GRAMPUS 

221600050113 PARTITION;FLAT,320MM*290MM,BC FL 

221673150004 PARTITION;PALLET,8060 

MiTac Secret 


136



221503250002 PARTITION;TOP/BTM,BATTERY,GRAMPU 

412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ 

412673800002 PCB ASSY;WIRELESS LAN CARD,MINI 

316673100003 PCB;PWA-8060/AUDIO BD R01 

316504100002 PCB;PWA-8060/BATT GAUGE BD 

316504100001 PCB;PWA-8060/BATT PROTECTION BD 

316673100004 PCB;PWA-8060/BUTTON BD R01A 

316673100002 PCB;PWA-8060/DD BD R01 

316673100001 PCB;PWA-8060/MOTHER BD R01 

316000000019 PCB;PWA-STINGRAY/INVERTER BD (FO 

222670820003 PE BAG;L560*W345,7521N 

222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS 

230000000003 PEN;OIL,BLUE,PRC 

340673100025 PLATE ASSY;CPU,8060 

411673100007 PWA;PWA-8060,AUDIO BD 

411673100006 PWA;PWA-8060,D/D BD,SMT 

411673100012 PWA;PWA-8060,D/D BD,T/U 

411673100001 PWA;PWA-8060,MOTHER BD 

411673100003 PWA;PWA-8060,MOTHER BD,SMT 

411673100002 PWA;PWA-8060,MOTHER BD,T/U 

411673100004 PWA;PWA-8060,T/P BD,SMT 

411673100011 PWA;PWA-8060,T/P BD,T/U 

411504100003 PWA;PWA-8060/BATT GAUGE BD,LI 

411504100001 PWA;PWA-8060/BATT PROTECTION BD, 

411504100002 PWA;PWA-8060/BATT PROTECTION BD, 



MiTac Secret 


411503400205 PWA;PWA-STINGRAY/INVERTER BD,MSL 

411503400206 PWA;PWA-STINGRAY/INVERTER BD,SMT 

332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC 

271045047101 RES;.004,1W,1%,2512,SMT PR1,PR2,PR504,PR505 

271045087101 RES;.008 ,1W ,1% ,2512,SMT PR501 

271045107101 RES;.01 ,1W ,1% ,2512,SMT PR504 

271045157101 RES;.015 ,1W ,1% ,2512,SMT PR41,PR43 

271046257101 RES;.025 ,2W ,1% ,2512,SMT,PRC R18,R18A 

271045357101 RES;.035,1W,1%,2512,SMT PR42 

271045087102 RES;.08,1W,1%,2512,SMT PR68,PR69 

271002000301 RES;0 ,1/10W,5% ,0805,SMT L503,PR40 

271071000002 RES;0 ,1/16W,0603,SMT PR13,PR29,PR30,PR39,PR5,PR50 

271071000002 RES;0 ,1/16W,0603,SMT R508 

271071000002 RES;0 ,1/16W,0603,SMT PR1,PR503,PR6,PR7,R58 

271071010301 RES;1 ,1/16W,5% ,0603,SMT PR535,PR536 

271072102111 RES;1.02K,1/10W,1% ,0603,SMT R202 

271071122102 RES;1.2K ,1/16W,1% ,0603,SMT PR4 

271071152101 RES;1.5K ,1/16W,1% ,0603,SMT R25,R26 

271071182101 RES;1.8K ,1/16W,1% ,0603,SMT R617 

271071100302 RES;10 ,1/16W,5% ,0603,SMT PR20,PR21,PR22,PR23,PR503,PR 

271071100302 RES;10 ,1/16W,5% ,0603,SMT R9 

271071102211 RES;10.2K,1/16W,1% ,0603,SMT R5 

271071101101 RES;100 ,1/16W,1% ,0603,SMT R507,R510,R524 

271071101301 RES;100 ,1/16W,5% ,0603,SMT R127,R179,R691 

271071101301 RES;100 ,1/16W,5% ,0603,SMT R37 

137



271071104101 RES;100K ,1/16W,1% ,0603,SMT PR45,PR47,PR48,PR515,PR534,P 

271071104101 RES;100K ,1/16W,1% ,0603,SMT R16,R17 

271071104101 RES;100K ,1/16W,1% ,0603,SMT R7 

271071104302 RES;100K ,1/16W,5% ,0603,SMT PR522,PR63,PR65,PR71,PR72,R1 

271071104302 RES;100K ,1/16W,5% ,0603,SMT R1,R2 

271071104302 RES;100K ,1/16W,5% ,0603,SMT PR13 

271071104302 RES;100K ,1/16W,5% ,0603,SMT R38,R44,R48 

271071104302 RES;100K ,1/16W,5% ,0603,SMT R11,R15,R2,R8,R9 

271071103101 RES;10K ,1/16W,1% ,0603,SMT PR25,PR28,PR35 

271071103101 RES;10K ,1/16W,1% ,0603,SMT PR14,PR506 

271071103101 RES;10K ,1/16W,1% ,0603,SMT R18 

271071103302 RES;10K ,1/16W,5% ,0603,SMT PR3,PR31,R105,R106,R131,R134, 

271071103302 RES;10K ,1/16W,5% ,0603,SMT R507 

271071103302 RES;10K ,1/16W,5% ,0603,SMT PR4 

271071103302 RES;10K ,1/16W,5% ,0603,SMT R3,R4 

271071106301 RES;10M ,1/16W,5% ,0603,SMT R129,R130 

271071113001 RES;113 ,1/16W,1% ,0603,SMT R537 

271071113101 RES;11K ,1/16W,1% ,0603,SMT PR17 

271071121211 RES;12.1K,1/16W,1% ,0603,SMT PR537,PR54 

271071151101 RES;150 ,1/16W,1% ,0603,SMT R2,R528,R531,R554,R555 

271071154101 RES;150K ,1/16W,1% ,0603,SMT R1 

271071153101 RES;15K ,1/16W,1% ,0603,SMT R3,R4 

271071153301 RES;15K ,1/16W,5% ,0603,SMT R124,R133,R27,R28,R511,R512,R6 

271071153301 RES;15K ,1/16W,5% ,0603,SMT PR15,PR505 

271071164301 RES;160K ,1/16W,5% ,0603,SMT R42 



MiTac Secret 


271071169311 RES;169K ,1/16W,1% ,0603,SMT PR558 

271071181102 RES;18.2,1/16W,1% ,0603,SMT R609 

271071102102 RES;1K ,1/16W,1% ,0603,SMT PR553,R67,R70 

271071102102 RES;1K ,1/16W,1% ,0603,SMT R8,R15,R19 

271071102302 RES;1K ,1/16W,5% ,0603,SMT PR19,PR542,PR557,PR67,R122,R 

271071102302 RES;1K ,1/16W,5% ,0603,SMT PR11,PR9,R2 

271071102302 RES;1K ,1/16W,5% ,0603,SMT R35,R39,R43 

271071105101 RES;1M ,1/16W,1% ,0603,SMT PR506,PR545,R166 

271071105101 RES;1M ,1/16W,1% ,0603,SMT R13 

271071105301 RES;1M ,1/16W,5% ,0603,SMT PR12,PR16,PR18,PR525,PR526,P 

271071105301 RES;1M ,1/16W,5% ,0603,SMT PR18 

271071105301 RES;1M ,1/16W,5% ,0603,SMT R40 

271071222302 RES;2.2K ,1/16W,5% ,0603,SMT R149,R151,R527,R539,R704,R705 

271071225301 RES;2.2M,1/16W,5% ,0603,SMT R34,R36 

271034278301 RES;2.7 ,1/2W ,5% ,2010,SMT R697 

271071272301 RES;2.7K ,1/16W,5% ,0603,SMT PR24,R174 

271071272301 RES;2.7K ,1/16W,5% ,0603,SMT PR16 

271071201301 RES;200 ,1/16W,5% ,0603,SMT R1,R12,R16,R17,R22,R25,R3,R31, 

271071201301 RES;200 ,1/16W,5% ,0603,SMT R14,R17 

271071204101 RES;200K ,1/16W,1% ,0603,SMT PR8 

271071203101 RES;20K ,1/16W,1% ,0603,SMT PR518,PR532 

271071203101 RES;20K ,1/16W,1% ,0603,SMT R2 

271071203302 RES;20K ,1/16W,5% ,0603,SMT PR502 

271071221302 RES;22 ,1/16W,5% ,0603,SMT R186,R187,R211,R221,R222,R223 

271071224301 RES;220K ,1/16W,5% ,0603,SMT R46,R536 

138



271071223302 RES;22K ,1/16W,5% ,0603,SMT PR519,R164 

271071228102 RES;22K,1/16W,1%,0603,SMT PR520 

271071228102 RES;22K,1/16W,1%,0603,SMT PR19 

271071237311 RES;237K ,1/16W,1% ,0603,SMT PR517 

271071249811 RES;24.9 ,1/16W,1% ,0603,SMT R43,R523 

271071244301 RES;240K ,1/16W,5% ,0603,SMT R41 

271071267211 RES;26.7K,1/16W,1% ,0603,SMT PR26 

271071270301 RES;27 ,1/16W,5% ,0603,SMT R8 

271071274811 RES;27.4 ,1/16W,1% ,0603,SMT R69 

271071205101 RES;2M ,1/16W,1% ,0603,SMT R11 

271071301301 RES;300 ,1/16W,5% ,0603,SMT R608 

271071301011 RES;301 ,1/16W,1% ,0603,SMT R115,R116,R34,R526,R530,R60,R6 

271071301311 RES;301K ,1/16W,1% ,0603,SMT PR550 

271071330302 RES;33 ,1/16W,5% ,0603,SMT PR546,R111,R112,R113,R19,R192 

271071334301 RES;330K ,1/16W,5% ,0603,SMT R152,R233 

271071333301 RES;33K ,1/16W,5% ,0603,SMT R794,R796 

271071365811 RES;36.5 ,1/16W,1% ,0603,SMT R114,R53 

271071374211 RES;37.4K,1/16W,1% ,0603,SMT PR529 

271071390302 RES;39 ,1/16W,5% ,0603,SMT R20 

271071393302 RES;39K ,1/16W,5% ,0603,SMT C727,C739 

271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR539,PR548 

271071472101 RES;4.7K ,1/16W,1% ,0603,SMT PR544 

271071472101 RES;4.7K ,1/16W,1% ,0603,SMT PR2 


271071472302 RES;4.7K ,1/16W,5% ,0603,SMT R501,R506 



MiTac Secret 


271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR531,R636 

271071402811 RES;40.2 ,1/16W,1% ,0603,SMT R42 

271071402311 RES;402K ,1/16W,1% ,0603,SMT PR53 

271071432211 RES;43.2K,1/16W,1% ,0603,SMT PR49,PR521 

271071442311 RES;442K,1/16W,1% ,0603,SMT PR27 

271071471101 RES;470 ,1/16W,1% ,0603,SMT R21,23,27 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R551,R601,R603 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R510 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R3,R4,R5,R502,R503,R504,R505,R 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R1 

271071474301 RES;470K ,1/16W,5% ,0603,SMT PR37,PR38,PR44,PR523,PR524,P 

271071474301 RES;470K ,1/16W,5% ,0603,SMT PR12,PR502 

271071475011 RES;475 ,1/16W,1% ,0603,SMT R580 

271071475311 RES;475K ,1/16W,1% ,0603,SMT PR64 

271071473301 RES;47K ,1/16W,5% ,0603,SMT PR66,R101,R103,R107,R142,R154 

271071487211 RES;48.7K,1/16W,1% ,0603,SMT PR33 

271071487211 RES;48.7K,1/16W,1% ,0603,SMT R7 

271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R117,R119,R508,R509,R515,R516 

271071499211 RES;49.9K,1/16W,1% ,0603,SMT PR46 

271071518301 RES;5.1 ,1/16W,5% ,0603,SMT PR5 

271071512101 RES;5.1K ,1/16W,1% ,0603,SMT R201 

271002515302 RES;5.1M ,1/8W ,5% ,0805,SMT,PRC R10 


271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R45 


139



271071511812 RES;51.1,1/16W,1% 0603,SMT R35,R514 


271071561101 RES;560 ,1/16W,1% ,0603,SMT PR34 

271071561101 RES;560 ,1/16W,1% ,0603,SMT R22,24,28 

271071563101 RES;56K ,1/16W,1% ,0603,SMT PR36 

271071634111 RES;6.34K,1/16W,1% ,0603,SMT R167 

271071682301 RES;6.8K ,1/16W,5% ,0603,SMT R513 

271071631101 RES;63.4,1/16W,1% ,0603,SMT R68 

271071681101 RES;680 ,1/16W,1% ,0603,SMT R506 

271071681101 RES;680 ,1/16W,1% ,0603,SMT R501 

271071683101 RES;68K ,1/16W,1% ,0603,SMT R12 

271071683301 RES;68K ,1/16W,5% ,0603,SMT R173 

271071698311 RES;698K ,1/16W,1% ,0603,SMT R5 

271071750302 RES;75 ,1/16W,5% ,0603,SMT R11,R501,R502,R619,R624 

271071750311 RES;750K,1/16W,1% ,0603,SMT PR511 

271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R220,R550,R552,R618,R679,R93,R 

271071887111 RES;8.87K,1/16W,1% ,0603,SMT PR3 

271071887211 RES;88.7K,1/16W,1% ,0603,SMT R6 

271071953212 RES;9.53K,1/16W,1%,0603,SMT PR507 

271071909011 RES;909 ,1/16W,1% ,0603,SMT R14 

451673100001 ROM ME KIT;8060 

271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP531,RP532,RP535,RP536 

271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM RP16,RP17 

271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP501,RP502 

271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT RP1 



MiTac Secret 


271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP528,RP533 

271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP11,RP529 

271571330301 RP;33*8 ,16P ,1/16W,5% ,1606,SM RP10,RP12,RP13,RP14,RP15,RP5 

271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP23 

271621472303 RP;4.7K*8,10P,1/16W,5% ,1206,SMT RP20 

271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP21,RP527 

271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT RP508,RP509,RP510,RP511,RP51 

271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP4,RP530 

271621822302 RP;8.2K*8,10P,1/32W,5% ,1206,SMT RP522,RP523,RP525,RP526 

345669900001 RUBBER FOOT;7170 

345673100005 RUBBER;LCD DOWN,8060 

345673100006 RUBBER;LCD UP,8060 

345671200002 RUBBER;MIDDLE,LCD,8170 

565167310001 S/W;CD ROM,SYSTEM DRIVER,8060 

565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO 

565167000013 S/W;CD-ROM,B'S RECORDER GOLD2.0 

371102030303 SCREW;M2L3,K-HEAD(+),NIW/NLK 

340673100024 SHIELDING ASSY;HDD,8060 

340673100026 SHIELDING ASSY;IO,8060 

333020000003 SHRINK TUBE;600V,105'C,D0.8*5MM, 

333050000107 SHRINK TUBE;UL,600V,105'C,ID2.5* 

561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 

361400003021 SOLDER CREAM;NOCLEAN,P4020870980 

365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14 

600100010010 SOLDER WIRE;63/37,0.5,CM,N/C,PRC 

140



370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 

370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 

370102631202 SPC-SCREW;M2.6L6,K-HD,NIW/NLK 

370102631202 SPC-SCREW;M2.6L6,K-HD,NIW/NLK 

370102010201 SPC-SCREW;M2L2,NIW,K-HD,t=0.8,NL 

370102010253 SPC-SCREW;M2L2.5,NIW/NLK,HD07 

370102020301 SPC-SCREW;M2L3,NIW,K-HEAD 



370102010404 SPC-SCREW;M2L4,K-HD,NIB 

370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 

340673100017 SPEAKER ASSY;LEFT,8060 

340673100018 SPEAKER ASSY;RIGHT,8060 

346673100015 SPONGE;DDB,SWITCH,8060 

341673100007 SPRING SCREW;HEATSINK,8060 

342673100014 STAND OFF;M2L8.3,CASHI,8060 

342673100018 STAND OFF;MDC,8060 

337040100005 SW;PUSH BUTTON,SPST,12V50MA,RA,H SW501,SW502,SW503,SW504,SW 

297040100002 SW;PUSH BUTTON,SPST,4P,15V/20mA, SW1,SW2 

297040100002 SW;PUSH BUTTON,SPST,4P,15V/20mA, SW1 

225000020002 TAPE;1/2",2 ADHESIVE FACE,20YARD 

622200000008 TAPE;CARTON,2.5"W,30M/RL,PRC 

225600000054 TAPE;INSULATING,POLYESTER FILM,1 

310111130319 THERMISTOR;10K,1%,RA,0603,1P,SEM R198 

310111103011 THERMISTOR;10K,1%,RA,DISK,103AT- T1 



MiTac Secret 


442673100051 TOUCH PAD MODULE;TM41P-311,SYNAP 

288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ1,PQ13,PQ2,PQ3,PQ4,PQ501,P 

288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ2,PQ3 

628820014401 TRANS;DTA144EKA,PNP,100MA,50V,SO Q6,Q7 

288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 PQ11,Q14,Q2,Q505,Q506,Q507,Q 

288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q502 

288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ14,PQ511,Q12,Q5,Q9 

288203904010 TRANS;MMBT3904L,NPN,Tr35NS,TO236 Q4,Q503,Q504 

288203906002 TRANS;MMBT3906L,40V,200mA,SOT23, Q1 

328202003001 TRANS;MTD20N03HDL,N-MOSFET,2A,30 PQ16 

288200351001 TRANS;NDS351,N-MOSFET,.25HM,SOT- Q10,Q11 

288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 PQ15,PQ8,Q1,Q8 

288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 Q501 

288202303001 TRANS;SI2303DS,P-MOSFET,SOT-23 PQ5,Q3 

288202304001 TRANS;SI2304DS,N-MOSFET,SOT-23 Q13 

288104362001 TRANS;SI4362DY,N-HOSFET,S08 PU1,PU12,PU2,PU3,PU4,PU509,P 

288104362001 TRANS;SI4362DY,N-HOSFET,S08 PU3,PU503 

288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,.02 Q2,Q2A,Q3,Q3A 

288204532001 TRANS;SI4532DY,N&P-MOSFET,SO8,PR U2 

288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU11,PU19,PU511,PU512,PU8 

288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU1,PU2,PU6 

288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU14,PU17,PU7 

288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ12,PQ9,PU18,PU20,PU24,PU5 

288204892001 TRANS;SI4892DY,N-MOSFET,SO8 PU15,PU501,PU502,PU503,PU50 

288204892001 TRANS;SI4892DY,N-MOSFET,SO8 PU5,PU502 

141



288209410001 TRANS;SI9410DY,N-MOSFET,.04OHM,S Q514 

273001050022 TRANSFORMER;10/100 BASE,PH163112 U7 

270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-0 S1 

634615190001 WASHER;D7.5,PWR-48B-12A 

421666200009 WIRE ASSY;BATTERY BIOS,NV 

421668300005 WIRE ASSY;BIOS,BATTERY,HOPE J21 

422673100004 WIRE ASSY;INVERTOR,LCD,8060 

422673100005 WIRE ASSY;MDC,8060 

422673100007 WIRE ASSY;MIC,8060 

422673100001 WIRE LCD ASSY;LCD,8060 

332110020061 WIRE;#20,UL1007,120MM,RED,PRC 

332110020044 WIRE;#20,UL1007,65MM,BLACK,PRC 

332110020053 WIRE;#20,UL1007,65MM,RED,PRC,752 

332110026115 WIRE;#26,UL1007,45MM,BLACK,PRC 

332110026078 WIRE;#26,UL1007,65MM,YELLOW,PRC 

332110026116 WIRE;#26,UL1007,81MM,WHITE,PRC 

273001050062 XSFORMER;CI8.5,SIT16260,16/2600T T1 

274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X3 

274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X503 

274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X504,X6 

274012400407 XTAL;24M,20PPM,16PF,7.5*5,4P,SMT X5 

274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X502 

274012700401 XTAL;27MHZ,20PPM,16PF,7*5,4P,SMT X1 

274013276114 XTAL;32.768KHZ,10PPM,12.5PF X4 

274010800401 XTAL;8MHZ ,30PPM,16PF,7*5,4P,SMT P/N:526267310005 


MiTac Secret 


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MiTac Secret 


Reference Material 

Intel Mobile Pentium 4 Processor – M 

Intel 82845 Memory Controller Hub Mobile (MCH-M) 

Intel 82801CAM I/O Controller Hub 3 (ICH3-M) 

RTL8139C(L) Ethernet Controller 

PCI4410 PCMCIA Controller 

8060 Hardware Engineering Specification 

Intel, INC 

Intel, INC 

Intel, INC 

Realtek Semiconductor, INC 

TI, INC 

Technology Corp./MiTAC

SERVICE MANUAL FOR 8060 

Sponsoring Editor : Jesse Jan 

Author : Sissel Diao 

Assistant Editor : Janne Liu 

Publisher : MiTAC International Corp. 

Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. 

Tel : 886-3-5779250 Fax : 886-3-5781245 

First Edition : Dec. 2002 

E-mail : Willy.Chen @ mic.com.tw 

Web : http: //www.mitac.com http: //www.mitacservice.com

Mitac 8060 Service Manual - laptop schematics, notebook ...

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