THE NON-VOLATILE FPGA GUIDE LATTIcE XO, XO2 AND XP2

THE NON-VOLATILE FPGA GUIDE
LATTIcE XO, XO2 AND XP2
11/2010

MAcHXO FAMILY
crossover Programmable Logic Devices
The MachXO family of non-volatile, infinitely
reconfigurable Programmable Logic Devices (PLDs) is
designed for applications traditionally implemented using
CPLDs or low-capacity FPGAs. The MachXO family combines
an optimised Look-Up Table (LUT) fabric with Lattice’s ispXP
technology to provide the high pin-to-pin performance
and instant-on associated with CPLDs, with the flexibility of
FPGAs, all in a low-cost device.
The MachXO family offers a high pin-to-logic ratio that is
ideal for glue logic, bus bridging, bus interfacing, powerup
control and control logic. In addition, MachXO devices
feature Lattice‘s exclusive sysCLOCK PLLs, sysMEM
embedded memory blocks (EBRs) and high-performance I/Os.
These features further facilitate the design of high-speed
systems. Designs for MachXO can easily be completed with
Lattice‘s free ispLEVER ® Starter design software.
Key Features and Benefits
Non-Volatile, Infinitely Reconfigurable
• Instant-on, powers up in less than 1 mS
• Single-chip, no external configuration memory
• Excellent design security, no bit stream to intercept
2
Performance to 3.5ns Pin-to-Pin
TransFR Technology Allows Simple Field Upgrades
Flexible LUT Architecture
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
Embedded and Distributed Memory
• Up to 27.6 Kbits sysMEM Embedded Block RAM
• Includes dedicated FIFO control logic
• Up to 7.7 Kbits distributed RAM
Flexible I/O Buffer
• Programmable sysIO buffer supports wide range of
interfaces:
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
• PCI*
• LVDS*, Bus-LVDS*, LVPECL*, RSDS*
sysCLOCK PLLs
• Up to two analog PLLs per device
• Clock multiply, divide and phase shifting
Sleep Mode Reduces Standby Power to

MAcHXO Block Diagram
sysClock PLLs for
clock management
sysMEM Embedded
Block RAM (EBR)
provides 9 kbit true dual port
RAM at up to 275 MHz
Programmable Function
Unit (PFU) with RAM
JTAG Port
for configuration Flash
and SRAM memory
JTAG
SysMEM Embedded Block RAM (EBR)
MachXO1200 and MachXO2280 devices include flexible
sysMEM EBR blocks. sysMEM EBR blocks provide on-chip
memory resources to support a broad range of features.
• Up to 27.6 K Bits sysMEM Embedded Block RAM (EBR)
• 275 MHz Operation
• Configurable Width and Depth
• Single Port, Dual Port and Pseudo-Dual Port
• Dedicated Logic for FIFO Control
• Bus Size Matching
• RAM Initialisation and User ROM Operation
• Memory Cascading
MachXO devices bring together
the best features of FPGAs and
CPLDs ... low cost, outstanding
pin-to-pin performance, and
instant-on start-up. Plus, MachXO devices are available in
space-saving, RoHS-compliant packaging.
Flash Memory
sysMEM configuration
Single Port Dual Port Pseudo-Dual Port FIFO
8192 x 1 8192 x 1 8192 x 1 8192 x 1
4096 x 2 4096 x 2 4096 x 2 4096 x 2
2048 x 4 2048 x 4 2048 x 4 2048 x 4
1024 x 9 1024 x 9 1024 x 9 1024 x 9
512 x 18 512 x 18 512 x 18 512 x 18
256 x 36 – 256 x 36 256 x 36
Upgrade
Flash
FLASH
(Configuration 2)
Logic – SRAM
(Configuration 1)
Program Flash in background
while logic functions
On-chip Flash Memory offers
instant-on start-up and security
from bitstream snooping
Flexible Routing optimised for
speed, low-cost, and routability
Programmable Function Unit
without RAM (PFF)
sysIO Buffers support LVCMOS /
LVTTL, LVDS and PCI
FLASH
(Configuration 2)
Upgrade
SRAM
Logic – SRAM
(Configuration 2)
JTAG commands control I/O & logic
states while Flash is copied to SRAM
– Device is operational in

MAcHXO FAMILY
MachXo Device Selection Guide
4
Feature LcMXO256 LcMXO640 LcMXO1200 LcMXO2280
LUTs 256 640 1200 2280
Distributed RAM (Kbits) 2 6.1 6.4 7.7
Embedded Block RAM – EBR (Kbits) – – 9.2 27.6
Number of EBR Blocks – – 1 3
V CC Voltage (V) Options 1.2 V or 1.8 / 2.5 / 3.3 V 1.2 V or 1.8 / 2.5 / 3.3 V 1.2 V or 1.8 / 2.5 / 3.3 V 1.2 V or 1.8 / 2.5 / 3.3 V
Number of PLLs – – 1 2
Number of I/O Banks 2 4 8 8
Maximum Number of I/Os 78 159 211 271
Maximum Number of LVDS Pairs* – – 27 33
Packages & I/O combinations
100-pin TQFP (14 x 14 mm)** 78 74 73 73
144-pin TQFP (20 x 20 mm) 113 113 113
100-ball csBGA (8 x 8 mm) 78 74
132-ball csBGA (8 x 8 mm) 101 101 101
256-ball caBGA (14 x 14 mm) 159 211 211
256-ball ftBGA (17 x 17 mm) 159 211 211
324-ball ftBGA (19 x 19 mm) 271
* Number of LVDS outputs can be increased by emulating with external resistors. ** In the 100-pin TQFP package, designs can not migrate from LCMXO640 to 1200.
LA-MachXo Automotive Family Selection Guide
Feature LAMXO256E/c LAMXO640E/c LAMXO1200E LAMXO2280E
LUTs 256 640 1200 2280
Dist. RAM (Kbits) 2.0 6.0 6.25 7.5
EBR SRAM (Kbits) 0 0 9.2 27.6
Number of EBR SRAM Blocks (9 Kbits) 0 0 1 3
V CC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2 1.2
Number of PLLs 0 0 1 2
Max. I/O 78 159 211 271
Packages
100-pin Lead-Free TQFP (14x14 mm) 78 74 73 73
144-pin Lead-Free TQFP (20x20 mm) 113 113 113
256-ball Lead-Free ftBGA (17x17 mm) 159 211 211
324-ball Lead-Free ftBGA (19x19 mm) 271

MAcHXO2 FAMILY
Optimised for consumer and System control
Applications
The MachXO2 family of non-volatile infinitely reconfigurable
Programmable Logic Devices (PLDs) is designed for low-power
consumer applications such as smart phones, GPS devices
and PDAs, as well as for system control applications found in
telecommunications infrastructure, computing, industrial and
medical equipment. Combining an optimized lookup table (LUT)
architecture with 65-nm embedded Flash process technology,
MachXO2 devices provide a flexible “do-it-all” solution for designs.
The MachXO2 family offers system designers the benefits of
increased system integration, improved system robustness and
reduced static power consumption. In addition, the MachXO2
family includes hardened implementations of some of the most
popular functions used in system control applications such as User
Flash Memory (UFM), I 2 C, SPI and timer/counter. Thus, through the
provision of these features, the MachXO2 family offers customers a
“do-it-all PLD”.
MachXO2 devices are available in three options: high performance
(HC, HE) and ultra-low power (ZE).
MachXO2 control Application Example
Control
µP
µP
µP
ASIC
ASSP
Custom, I 2 C
SPI, LPC
MachXO2
Bus
Interface
Status
Registers
Power
Sequence
& Reset
LPC
GPIO
Delta
Sigma/
PWM
Flash
Controller
Serial
Bus
Bridges
I 2 C
SPI
1 2 3 4
Flash
5

MAcHXO2 FAMILY
Three Product Options – More Flexibility
Focus Option Regulator
6
Nominal
Vcc (V)
Internal
Vcc (V)
Low Power ZE – 1.2 1.2 60
High HC 3.3, 2.5 1.2 150
Performance HE – 1.2 1.2 150
System
Performance (MHz)
Key Features and Benefits
Large Number of I/Os
• Up to 335 I/Os with broad range of package options
Robust Architecture For Reliable Operation
• Instant-on, powers up in less than 1 ms
• Operate from a single 3.3 / 2.5 / 1.2 V supply
• Input hysteresis allows operation in noisy environment
Enhanced Security
• Unique device Trace ID
• One-time-programmability
High Functional Integration For Cost Reduction
• Densities ranging from 256 to 6864 LUTs
• Up to 240 Kbits sysMEM Embedded Block RAM
• Up to 54 Kbits Distributed RAM
• Up to 256 Kbits of user Flash memory
• Hardened I 2 C, SPI, timer/counter functions
• Robust PLL with fractional division
Flexible sysIO Buffer
• Support for LVCMOS, LVTTL, LVDS, SSTL, HSTL interfaces
• Hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Pre-Engineered Source Synchronous I/O
• Dedicated gearing logic (7:1, 4:1, 8:1)
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR with DQS support
Broad Device Offering
• Commercial: 0 to 85 ºC (TJCOM)
• Industrial: -40 to 100 ºC (TJIND)
System Level Support
• Reliable field updates with TransFR and Dual Boot
• Security options include security bits, One Time
Programmable (OTP) mode and unique device TraceID
• IEEE 1532 Compliant In-System Programming
• IEEE Standard 1149.1 boundary scan
Ultra Low Power For Long Battery Life
• As low as 19 μW static power
• Manage power with power guard and power controller
features

MAcHXO2
ARcHITEcTURE
Architecture Overview
MachXO2 PLDs are designed to offer an unprecedented mix
of low cost, low power and high functionality in a single
device. Through the use of 65-nm Flash technology and
innovative design, MachXO2 devices ultra low-power, small
footprint, high system performance, a robust architecture,
support for enhanced I/O features, on-chip UFM, hardened
control functions and flexible security features.
MachXO2 Block Diagram
sysCLOCK PLLs
for frequency
synthesis & clock
alignment
Programmable
Function Units
(PFUs) with RAM
sysMEM Block
9 Kbit Dual Port
RAMs
Advanced clocking Technology
• Full featured PLL
• Fractional division improves frequency synthesis
• 10 to 400 MHz operation
• On-chip oscillator with +/-5% accuracy over PVT and
2 to 133 MHz operation
Flash Memory
sysMEM configuration Options
Single
Port
Dynamic
Phase
Adjust
Feedback
Divider
True Dual
Port
Embedded Functional Block
offers hardened SPI, I 2 C, and
timer / counter
UFM (User Flash Memory)
On-chip Flash Memory
provides instant-on, high
security & single chip solution
sysIO Buffers
support a wide range of interfaces
including source synchronous I/Os.
I/O logic supports 7:1 input gearing.
Input
Divider
Fractional
-N
Synthesizer
sysCLOCK PLL
Phase
Freq.
Detect
Pseudo-
Dual Port
VCO
Output
Divider
Output
Divider
Output
Divider
Output
Divider
FIFO
8192 x 1 8192 x 1 8192 x 1 8192 x 1
4096 x 2 4096 x 2 4096 x 2 4096 x 2
2048 x 4 2048 x 4 2048 x 4 2048 x 4
1024 x 9 1024 x 9 1024 x 9 1024 x 9
512 x 18 512 x 18
Phase
Adjust
Edge
Trim
Phase
Adjust
Edge
Trim
Phase
Adjust
Edge
Trim
Phase
Adjust
Edge
Trim
7

MAcHXO2
ARcHITEcTURE
On-chip User Flash Memory
sysIO Buffers Support
• Programmable sysIO supports wide range of interfaces:
• LVTTL, LVCMOS (3.3/2.5/1.8/1.5/1.2)
• PCI*, LVDS*, Bus-LVDS, MLVDS
• RSDS, LVPECL
• SSTL 25/18, HSTL 18
• Up to 256 Kbits
• Input hysteresis
• Hot socketing
• On-chip differential termination*
• Programmable pull-up, pull-down, bus keeper (I/O cell
defaults to pull-down during power-up)
• DDR registers in I/O cells
• Dedicated gearing logic
* Available on XO2-1200 and larger densities.
8
Read / Write from Fabric
UFM EBR
Logic
Configuration
FLASH
JTAG / SPI / I 2 C
Logic
Configuration
SRAM
MachXO2 Voltage Options
1.2 V 3.3 / 2.5 V 1.2 V
VCC VCCIO VCC VCCIO VCC VCCIO MachXO2
ZE
Embedded function block
Asymmetrical Banking
Scheme Increases Flexibility
Bank 3 Bank 4 Bank 5
MachXO2
HC
MachXO2
HE
SPI I 2 C I 2 C Timer
WISHBONE BUS
MachXO2 Fabric
Bank 0
MachXO2
Bank 2
Bank 1
Note: MachXO2-256, 640 & 1200 LUT devices
have four banks.

Easy, Reliable Field Updates
Lattice’s Transparent Field Reconfiguration (TransFR)
technology enables logic updates in the field without
interrupting the operation of the system.
Step 1
Program Flash in
background while
logic functions
Step 2
Precisely control
I/Os and initiate
Flash to SRAM
transfer through
JTAG.
Upgrade
Flash
FLASH
(Configuration 2)
Logic – SRAM
(Configuration 1)
FLASH
(Configuration 2)
Upgrade
SRAM
Logic – SRAM
(Configuration 2)
Dual Boot for Reliability
MachXO2 devices offer an additional level of reliability by
supporting dual boot with external SPI Flash.
Loads active configuration at power-up
FLASH
(Active Configuration)
Read
Data
LOGIC SRAM
Golden
Configuration
Control
If active configuration fails, then the
golden configuration is loaded
SPI
Configuration
Memory
Programming Options
MachXO2 devices offer several programming options,
including: JTAG IEEE 1149.1/1532, I2C Slave, and SPI
Master / Slave modes.
Flexible Security Options
MachXO2 devices support
optional security bits and a One-
Time-Programmable (OTP) mode
that prevents further erasure
or programming of the Flash
memory. A unique 64-bit device
TraceID can be used for tracking
purposes.
Broad Range of Space-Saving
Package Options
MachXO2 devices are available in a
wide range of advanced halogenfree
packages. MachXO2 devices
are designed to provide density
migration within the same package.
9

MAcHXO2
ARcHITEcTURE
Reference Design Portfolio
Lattice offers an expanding portfolio of IP cores and reference
designs targeted for system applications. Optimized for the
MachXO2 architecture, these include I2C, SPI, UART, PWM
fan control, LCD controller, and LatticeMico8 microcontroller.
The reference designs, source codes and documentation can
be downloaded for free from the Lattice website. For more
information, go to www.latticesemi.com/ip.
Device Selection Guide
Feature XO2-256 XO2-640 XO2-1200 XO2-2000 XO2-4000 XO2-7000
LUTs 256 640 1280 2112 4320 6864
Embedded RAM (Kbits) 0 18 64 74 92 240
Distributed RAM (Kbits) 2 5 10 16 34 54
UFM (Kbits) 0 24 64 80 96 256
PLL 0 0 1 1 2 2
Hardened Control Functions:
I 2 C (2), SPI (1), Timer / Counter (1)
Package I/O
25 WLCSP (2.5 x 2.5 mm, 0.4 mm)* 18
10
36 WLCSP (3.1 x 3.1 mm, 0.4 mm)* 29
64 μcBGA (4 x 4 mm, 0.4 mm) 45
100 TQFP (14 x 14 mm, 0.5 mm) 56 79 80 80
132 csBGA (8 x 8 mm, 0.5 mm) 56 80 105 105 105
144 TQFP (20 x 20 mm, 0.5 mm) 108 112 115 115
256 caBGA (14 x 14 mm, 0.8 mm) 207 207 207
256 ftBGA (17 x 17 mm, 1.0 mm) 207 207 207
332 caBGA (17 x 17 mm, 0.8 mm) 275 279
484 fpBGA (23 x 23 mm, 1.0 mm) 279 335
Typical Static Power
ZE (μW) 19 33 70 98 153 230
HC (mW) 4 7 13 18 32 48
HE (mW) 2 3 5
*Contact your Lattice sales representative for the support of WLCSP packages.

LATTIcEXP2 FAMILY
FlexiFLASH: Instant-on, Secure, Single-chip FPGA
LatticeXP2 devices combine a Look-up Table (LUT) based
FPGA fabric with Flash non-volatile cells in an architecture
referred to as flexiFLASH. The flexiFLASH approach
provides a single chip solution with benefits such as
instant-on operation, onchip storage featuring FlashBAK
embedded block RAM backup, access to general-purpose
Serial TAG memory and inherent design security. LatticeXP2
devices also support Live Update field reconfiguration with
TransFRTM, 128-bit AES bitstream encryption and Dual Boot
technologies.
The LatticeXP2 FPGA fabric utilizes an underlying
LatticeECP2 architecture that was optimized from the
outset with high performance and low cost in mind.
LatticeXP2 devices support 4-input LUT-based logic,
distributed and embedded memory, Phase Locked Loops
(PLLs), pre-engineered source synchronous I/O and enhanced
sysDSPTM blocks.
Lattice‘s ispLEVER ® design tool allows complex designs to
be efficiently implemented using the LatticeXP2 family of
FPGAs. The ispLEVER tool is complemented by pre-designed
IP (Intellectual Property) ispLeverCORE modules for the
LatticeXP2 family. By using these as standardized IP blocks,
designers are free to concentrate on the unique aspects of
their design, increasing their productivity.
Key Features and Benefits
• FlexiFLASH Architecture
• Instant-on (1 mS), single chip integration
• FlashBAK technology
• General-purpose Serial TAG memory
• Design security
• Live Update Technology
• TransFR technology – update logic configuration
while equipment continues to operate
• Dual Boot with external SPI Flash improves reliability
• Secure updates with 128 bit AES bitstream encryption
• Optimized FPGA Architecture
• Densities from 5K to 40K 4-input Look-up Tables (LUTs)
• Up to 885 Kbits sysMEM block RAM
• Up to 83 Kbits distributed RAM
• Low cost TQFP, PQFP and BGA packaging
• High Performance sysDSP Block
• Three to eight blocks with multiply and accumulate
• 12 to 32 18x18 multipliers
• Flexible sysIO Buffer Supports:
• LVCMOS 3.3/2.5/1.8/1.5/1.2; LVTTL
• SSTL 18 class I, II; SSTL 3/2 class I, II
• HSTL15 class I; HSTL18 class I, II
• PCI
• LVDS, Bus-LVDS, LVPECL
• Pre-engineered Source Synchronous Interfaces
• DDR / DDR2 up to 200 MHz / 400 Mbps
• 7:1 LVDS up to 600 Mbps
• Generic up to 750 Mbps
• Up to 4 sysCLOCK PLLs
• Standby Power Reduced by 33%
• System Level Support
• SPI/JTAG interface for device programming
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator for initialization & general use
• Soft Error Detect (SED) logic
• 1.2 V power supply core voltage
11

LATTIcEXP2 FAMILY
LatticeXP2 Block Diagram
12
On-chip Oscillator
sysIO Buffers support LVCMOS,
HSTL, SSTL, LVDS and more
sysMEM Embedded Block RAM
(EBR) provides up to 885 Kbit with
speeds up to 350 MHz.
sysDSP Blocks include multiply and
accumulate, up to 32 18x18 multipliers,
and speeds up to 325 MHz.
Programmable Function Unit
(PFU) provide up to 40 K LUTs and
speeds up to 350 MHz.
Architecture Overview
LatticeXP2 FPGAs combine on-chip Flash memory with
SRAM programmable LUTs and interconnect to provide
an optimized low cost architecture that delivers high
performance sysMEM embedded RAM blocks, distributed
memory, sysCLOCK PLLs, DDR memory interface, sysIO
buffers, and more.
FLASH
JTAG
FLASH
syscLOcK PLL Block Diagram
Control
Signals
Clock
Input
Clock
Feedback
Reset
Devider
Devider
Internal Feedback
Phase
Frequency
Detector/
Voltage
Control
Oscillator
Pre-Engineered Source
Synchronous I/O supports
DDR/DDR2 & 7:1 LVDS.
flexiFLASH architecture offers a secure,
instant-on, single chip solution.
JTAG and SPI Ports with Live
Update technology.
sysCLOCK Plls for clock
management. Up to 4 per device.
Devider
Phase/
Duty Cycle/
Duty Trim
Duty Trim
Devider
Lock Detect
÷3
Clock Outputs

sysIO Block Diagram
FPGA
Fabric
Phase
Frequency
Detector /
Voltage
Control
Oscillator
PFU Block Diagram
Tri-State
Register Block
(2 Flip / Flops)
Output
Register Block
(2 Flip / Flops)
Input
Register Block
(5 Flip / Flops)
DQS/Strobe Delay & Transition Detect
From
Routing
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
Carry Chain
Carry Chain
Slice 3
FF
Slice 2
FF
FF
FF
FF
Slice 1
FF
FF
FF
FF
Slice 0
FF
FF
FF
FF
To
Routing
sysDSP Block Diagram
Adder/
Multipliers Subtractor/
Accumulator
Summation
Input
Registers
sysMEM EBR Primitives
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
AD[12:0]
CLK
CE
RST
CS[2:0]
Pipeline
Registers
+ - Σ
+ - Σ
+
Output
Registers
Single Port RAM Dual Port RAM
ADA[12:0]
DIA[17:0]
CLKA
CEA
EBR DO[35:0]
EBR
RSTA
WEA
CSA[2:0]
DOA[17:0]
ROM Pseudo Dual Port RAM
ADW[12:0]
DI[17:0]
CLKW
EBR DO[35:0] CEW
WE
RST
CS[2:0]
EBR
ADB[13:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[13:0]
DO[35:0]
CER
CLKR
13

FLEXIFLASH: OVERVIEw
14
FPGA
Logic
Flash Memory
EBR Blocks
Flash
SPI /
JTAG
Port
FlashBAK technology allows storage of multipl data types:
error codes, data tables, and microprocessor code.
EBR Blocks
SRAM
Configuration Bits
EBR Blocks
Decryption & Device Lock
This approach provides a single chip solution, instant-on (1 mS),
FlashBAK EBR,TAG memory and design security.
FlashBAK Technology
Write to Flash during programming.
Write from Flash to EBRs during
configuration. Write from EBR to
Flash on user command.
Make infinite reads & writes to
EBR @ up to 350 MHz.
TAG
Memory
Flash Memory
JTAG
FPGA
Logic
SPI &
JTAG
Serial TAG Memory
Sequential
Address Counter
Fast parallel data transfer for
instant-on.
FLASH for single chip solution.
FlashBAK for sysMEM EBR storage.
Device lock for design security.
TDI TDO
Data Shift
Register (Nx8)
Flash
Memory
Array
JTAG
FPGA
Logic
Use Serial TAG Memory to store items such as Board ID, calibration
data, and manufacturing information.

LIVE UPDATE – FLEXILBLE, RENTABLE
AND SEcURE UPDATES
Live Update Technology
Field logic update continues to increase in importance in
a wide variety of applications due to the unprecedented
flexibility that it provides designers to fix bugs, respond to
changing standards, upgrade equipment and add additional
services. Lattice‘s Live Update technology allow logic to be
reliably updated in the field without interrupting system
operation
LatticeXP2
Flash
(Configuration 2)
Logic-SRAM
(Configuration 1)
LatticeXP2
Flash
(Configuration 2)
Logic-SRAM
(Configuration 1)
Step 1
While the device is
operating, Load New
Configuration (2) to
Configuration Memory
Step 2
Lock the I/Os in the Desired
States
Step 3
Transfer New Configuration
to Logic
Step 4
LatticeXP2 FPGA Regains
Control of I/Os
SPI Configuration
Memory
Read Data
LatticeXP2
Flash
(Active Config)
Backup
(Golden)
Configuration Logic-SRAM
Control
Minimize Field Calls Add Services Features Respond to Changeing Standards
Customer Site Head Office Customer Site
Transfer technology Dual boot for reliable update 128-bit AES bitstream encryption
If error detected in active configuration
then backup (golden) configuration is
loaded from SPI Flash.
128 Bit AES
Encrypted Bitstream
Decryption
Engine
128-Bit
Key
LatticeXP2
Flash
(Configuration)
Logic-SRAM
Design specific key stored in
on-chip Flash.
XP2 Device Selection Guide
Feature LFXP2-5 LFXP2-8 LFXP2-17 LFXP2-30 LFXP2-40
LUTs (K) 5 8 17 29 40
sysMEM EBR RAM Blocks 9 12 15 21 48
Embedded Memory (Kbits) 166 221 276 387 885
Distributed Memory (Kbits) 10 18 35 56 83
sysDSP Blocks 3 4 5 7 8
Number of 18x18 Multipliers 12 16 20 28 32
Number of PLLs 2 2 4 4 4
V Voltage (V) CC
Packages & I/O combinations
1.2 1.2 1.2 1.2 1.2
132-ball csBGA (8 x 8 mm) 86 86
144-pin TQFP (20 x 20 mm) 100 100
208-pin PQFP (28 x 28 mm) 146 146 146
256-ball ftBGA (17 x 17 mm) 172 201 201 201
484-ball fpBGA (23 x 23 mm) 358 363 363
672-ball fpBGA (27 x 27 mm) 472 540
15

DEVELOPMENT HARDwARE
MAcHXO USB connection Starter Kit
MACHXO USB connection Starter Kit is a complete hardware
kit, including everything required to program, evaluate and
de-bug a design for the Lattice MachXO architecture.
Product contents
• MACHXO USB Kit featuring:
• MachXO device: LCMXO640C-3TN144C
• Power via JTAG and USB
• Step-down-conversion for 3.3V
• 24 MHz oscillator
• 8 LEDs
• Power LED
• 4-input DIP switch
• USB-A connector incl. USB cable (A-A)
• Data-CD and Lattice Starter-SW
• Access to all device I/O
• Download via USB-connection
Ordering Information
Part Number: HWD-XO-USB
16
MAcHXO Development Kits
The MachXO Mini Development Kit is an easy to use, lowcost
platform to accelerate the evaluation of MachXO PLDs.
The kit features the MachXO LCMXO2280 device, 2 Mbit SPI
Flash and 1 Mbit SRAM memory, a temperature sensor, an
expansion header for I 2 C and SPI interfaces, and several LEDs
and user switches.
The MachXO Control Development Kit is a platform for
rapidly prototyping system control designs using MachXO
PLDs. The kit features the MachXO LCMXO2280 device,
Power Manager II ispPAC-POWR1014A, 2 Mbit SPI Flash and
1 Mbit SRAM memory, a temperature sensor, an expansion
header for I 2 C and SPI interfaces, and several LEDs and user
switches.
Ordering Information
Part Number:
LCMXO2280C-C-EVN
LCMXO2280C-M-EVN

MAcHXO2
Evaluation and Development Kits
MachXO2 Control
Development Board
MachXO2 Pico
Development Board
Lattice offers a number of evaluation and development
boards that provide a complete and easy-to-use platform
to evaluate the performance of the MachXO2, or aid in the
development of custom designs. For more information, go
to www.latticesemi.com/products/developmenthardware.
The following devices are available:
• MachXO 640c
• MachXO1200c
• MachXO2280c
and
• XP3c
• XP6c
• XP2-17E
• All devices in TQFP144
• 25 MHz oscillator
• 5 to 20 V external power supply
• 2 V 5 lin. voltage regulator for LVDS
• Power-LED
• JTAG connector 10 pol and 8 pol
• 8 LEDs
• Dimensions: 83 x 61 mm
Ordering information
Part Number:
LCMXO640C-eval-demo
LCMXO1200C-eval-demo
LCMXO2280C-eval-demo
LFXP3C-eval-demo
LFXP6C-eval-demoboard
HWDXP217EROHS
17

DEVELOPMENT HARDwARE
LATTIcEXP2 Advanced Evaluation Board
The LatticeXP2 Advanced Evaluation Board is a flexible
platform designed to help you quickly evaluate the
features and performance of the LatticeXP2 FPGA, or aid in
development of custom designs.
Product contents
LatticeXP2 Advanced Evaluation Board featuring
• LatticeXP2-17 FPGA in 484fpBGA package (LFXP2-17E-
18
4F484C)
• DDR2 SDRAM SO-DIMM socket (32-bit)
• Tri-speed Ethernet PHY (10/100/1G) / RJ45.
• PCI 32-bit edge
• LVDS Video Tx/Rx (via MDR-26 connectors)
• PS/2 I/O
• Compact Flash connector
• SMAs for clock and general purpose I/O
• A/D converter (ADS7842), D/A converter (DAC7617)
• USB host/controller
• Built-in USB download capability (includes MachXO device)
• RS-232 connector (female)
• on-board oscillator (dip socket)
• SPI flash memory for alternate configuration
• LCD connector
• 4 push-button switches, 8-bit switch
• 7-segment LED, 8 general purpose LEDs
• PAC1220AT8 for on-board power control
Ordering Information
Part Number: LFXP2-17E-H-EV
LATTIcEXP2 Standard Evaluation Board
The LatticeXP2 Standard Evaluation Board is a flexible
platform designed to help you quickly evaluate the
features and performance of the LatticeXP2 FPGA, or aid in
development of custom designs.
Product contents
LatticeXP2 Standard Evaluation Board featuring
• LatticeXP2-17 FPGA in 484fpBGA package (LFXP2-17E-
4F484C)
• On-board Asynch SRAM memory (256Kx32 providing
1Mbyte)
• A/D converter (ADS7842), D/A converter (DAC7617)
• 10K digital POT
• RS232 DB9 „female“ connector
• Compact Flash connector
• 8-bit switch, 4 push-button switches
• 7-segment LED, 8 general purpose LEDs
• Built-in USB download capability (includes MachXO device)
• Selectable I/O voltage
• SMA connectors for clock and general purpose I/O
• PAC607 power manager
• on-board oscillator (dip socket)
• Proto/test area
• SPI flash memory for alternate configuration
• Power via Bellnix DC power control modules
• LCD connector
Ordering Information
Part Number: LFXP2-17E-L-EV

PAcKAGE OFFERING
THE NON VOLATILE TEcHNOLOGY
Packages shown actual size. All dimensions refer to package body size.
64-BALL
ucBGA
4 x 4 mm
0.4 mm pitch
LAMXO XXXX X –
■ Device Family
LA-MachXO
Automotive
Crossover PLD
■ Logic Capacity
256 LUTs = 256
640 LUTs = 640
1200 LUTs = 1200
2280 LUTs = 2280
■ Supply Voltage
C = 1.8 V / 2.5 V / 3.3 V
E = 1.2 V
256-BALL
caBGA
8 x 8 mm
14 x 14 mm
14 x 14 mm
17 x 17 mm
0.5 mm pitch 0.5 mm pitch (100 TQFP) 0.8 mm pitch h 1.0 mm pitchh
LA-MACHXO Automotive
X XXXXXX X
■ Speed
3 = -3 Speed Grade
■ Package
TN100 = 100-pin Lead-Free TQFP
TN144 = 144-pin Lead-Free TQFP
FTN256 = 256-ball Lead-Free ftBGA
FTN324 = 324-ball Lead-Free ftBGA
■ Grade
E = Automotive
LATTICEXP2
LFXP2 XX E – X XXXXX X
■ Device Family
LatticeXP2
■ Logic Capacity
5 = 5 K LUTs
8 = 8 K LUTs
17 = 17 K LUTs
30 = 30 K LUTs
40 = 40 K LUTs
■ Supply Voltage
E = 1.2 V
■ Speed
5 = Slowest
6
7 = Fastest
Only MachXO256C(E), MachXO640C(E),MachXO1200E
and MachXO2280E are available for Automotive. LFXP2 - 5E / 8E / 17E also available for Automotive Speedgrade.
MACHXO
LCMXO XXXX X – X XXXXXX X
■ Device Family
MachXO PLD
■ Logic Capacity
256 LUTs = 256
640 LUTs = 640
1200 LUTs = 1200
2280 LUTs = 2280
■ Supply Voltage
C = 1.8 V / 2.5 V / 3.3 V
E = 1.2 V
■ Speed
3 = Slowest
4
5 = Fastest
■ Grade
C = Commercial
I = Industrial
100-/132-BALL
csBGA
Ordering information
■ Package
T100 = 100-pin TQFP
T144 = 144-pin TQFP
M100 = 100-pin csBGA
M132 = 132-ball csBGA
B256 = 256-ball caBGA
FT256 = 256-ball ftBGA
FT324 = 324-ball ftBGA
100-PIN
TQFP
T100 = 100-pin Lead-Free TQFP
T144 = 144-pin Lead-Free TQFP
M100 = 100-pin Lead-Free csBGA
M132 = 132-ball Lead-Free csBGA
BN256 = 256-ball Lead-Free caBGA
FT256 = 256-ball Lead-Free ftBGA
FT324 = 324-ball Lead-Free ftBGA
MACHXO2
LCMXO2 – XXXXX X X – X XXXXXX X
■ Device Family
MachXO2 PLD
■ Logic Capacity
256 = 256 LUTs
640 = 640 LUTs
1200 = 1280 LUTs
2000 = 2112 LUTs
4000 = 4320 LUTs
7000 = 6864 LUTs
■ Power/Performance
Z = Low Power
H = High Performance
■ Supply Voltage
C = 2.5 V / 3.3 V
E = 1.2 V
■ Grade
C = Commercial
I = Industrial
■ Package
M132 = 132-ball csBGA
FT256 = 256-ball ftBGA
F484 = 484-ball fpBGA
F672 = 672-ball fpBGA
MN132 = 132-ball Lead-Free csBGA
TN144 = 144-pin Lead-Free TQFP
QN208 = 208-pin Lead-Free PQFP
FTN256 = 256-ball Lead-Free ftBGA
FN484 = 484-ball Lead-Free fpBGA
FN672 = 672-ball Lead-Free fpBGA
■ Grade
C = Commercial
I = Industrial
■ Speed
1 = Slowest
2
3 = Fastest
4 = Slowest
5
6 = Fastest
Low Power
High Performance
256-BALL
ftBGA
■ Package
TG100 = 100-pin Halogen-Free TQFP
TG144 = 144-pin Halogen-Free TQFP
UMG64 = 64-ball Halogen-Free ucBGA
(0.4 mm Pitch)
MG132 = 132-ball Halogen-Free csBGA
(0.8 mm Pitch)
BG256 = 256-ball Halogen-Free caBGA
(0.8 mm Pitch)
FTG256 = 256-ball Halogen-Free ftBGA
(1.0 mm Pitch)
BG437 = 437-ball Halogen-Free caBGA
FG484 = 484-ball Halogen-Free fpBGA
(1.0 mm Pitch)
144-PIN
TQFP
20 x 20 mm
0.5 mm pitch
484-BALL fpBGA
23 x 23 mm
1.0 mm pitch
672-BALL
fpBGA
27 x 27 mm
1.0 mm pitch
208-PIN
PQFP
28 x 28 mm
0.5 mm pitch
332-Ball ll
caBGA
17 x 17 mm
0.8 mm pitch h
19

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