4 Instruction tables - Agner Fog

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Merom MULSD xmm,m64 1 1 1 1 float 1 MULPS xmm,xmm 1 1 1 float 4 1 MULPS xmm,m128 1 1 1 1 float 1 MULPD xmm,xmm 1 1 1 float 5 1 MULPD xmm,m128 1 1 1 1 float 1 DIVSS xmm,xmm 1 1 1 float 6-18 d) 5-17 d) DIVSS xmm,m32 1 1 1 1 float 5-17 d) DIVSD xmm,xmm 1 1 1 float 6-32 d) 5-31 d) DIVSD xmm,m64 1 1 1 1 float 5-31 d) DIVPS xmm,xmm 1 1 1 float 6-18 d) 5-17 d) DIVPS xmm,m128 1 1 1 1 float 5-17 d) DIVPD xmm,xmm 1 1 1 float 6-32 d) 5-31 d) DIVPD xmm,m128 1 1 1 1 float 5-31 d) RCPSS/PS xmm,xmm 1 1 1 float 3 2 RCPSS/PS xmm,m 1 1 1 1 float 2 CMPccSS/D xmm,xmm 1 1 1 float 3 1 CMPccSS/D xmm,m32/64 1 1 1 1 float 1 CMPccPS/D xmm,xmm 1 1 1 float 3 1 CMPccPS/D xmm,m128 1 1 1 1 float 1 COMISS/D UCOMISS/D xmm,xmm 1 1 1 float 3 1 COMISS/D UCOMISS/D xmm,m32/64 1 1 1 1 float 1 MAXSS/D MINSS/D xmm,xmm 1 1 1 float 3 1 MAXSS/D MINSS/D xmm,m32/64 1 1 1 1 float 1 MAXPS/D MINPS/D xmm,xmm 1 1 1 float 3 1 MAXPS/D MINPS/D xmm,m128 1 1 1 1 float 1 Math SQRTSS/PS xmm,xmm 1 1 1 float 6-29 6-29 SQRTSS/PS xmm,m 2 1 1 1 float 6-29 SQRTSD/PD xmm,xmm 1 1 1 float 6-58 6-58 SQRTSD/PD xmm,m 2 1 1 1 float 6-58 RSQRTSS/PS xmm,xmm 1 1 1 float 3 2 RSQRTSS/PS xmm,m 1 1 1 1 float 2 Logic AND/ANDN/OR/XORPS/D xmm,xmm 1 1 x x x int 1 0.33 AND/ANDN/OR/XORPS/D xmm,m128 1 1 x x x 1 int 1 Other LDMXCSR m32 14 13 1 42 STMXCSR m32 6 4 1 1 19 FXSAVE m4096 141 145 145 FXRSTOR m4096 119 164 164 Notes: d) Round divisors give low values. g) SSE3 instruction set. Page 92
Wolfdale Intel Core 2 (Wolfdale, 45nm) List of instruction timings and μop breakdown Explanation of column headings: Operands: i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm register, (x)mm = mmx or xmm register, sr = segment register, m = memory, m32 = 32-bit memory operand, etc. μops fused domain: μops unfused domain: p015: The total number of μops going to port 0, 1 and 5. p0: The number of μops going to port 0 (execution units). p1: The number of μops going to port 1 (execution units). p5: The number of μops going to port 5 (execution units). p2: The number of μops going to port 2 (memory read). p3: The number of μops going to port 3 (memory write address). p4: The number of μops going to port 4 (memory write data). Unit: Tells which execution unit cluster is used. An additional delay of 1 clock cycle is generated if a register written by a μop in the integer unit (int) is read by a μop in the floating point unit (float) or vice versa. flt→int means that an instruction with multiple μops receive the input in the float unit and delivers the output in the int unit. Delays for moving data between different units are included under latency when they are unavoidable. For example, movd eax,xmm0 has an extra 1 clock delay for moving from the XMM-integer unit to the general purpose integer unit. This is included under latency because it occurs regardless of which instruction comes next. Nothing listed under unit means that additional delays are either unlikely to occur or unavoidable and therefore included in the latency figure. Latency: Reciprocal throughput: The number of μops at the decode, rename, allocate and retirement stages in the pipeline. Fused μops count as one. The number of μops for each execution port. Fused μops count as two. Fused macro-ops count as one. The instruction has μop fusion if the sum of the numbers listed under p015 + p2 + p3 + p4 exceeds the number listed under μops fused domain. An x under p0, p1 or p5 means that at least one of the μops listed under p015 can optionally go to this port. For example, a 1 under p015 and an x under p0 and p5 means one μop which can go to either port 0 or port 5, whichever is vacant first. A value listed under p015 but nothing under p0, p1 and p5 means that it is not known which of the three ports these μops go to. This is the delay that the instruction generates in a dependency chain. The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating point operands are presumed to be normal numbers. Denormal numbers, NAN's and infinity increase the delays very much, except in XMM move, shuffle and Boolean instructions. Floating point overflow, underflow, denormal or NAN results give a similar delay. The time unit used is core clock cycles, not the reference clock cycles given by the time stamp counter. The average number of core clock cycles per instruction for a series of independent instructions of the same kind in the same thread. Integer instructions <strong>Instruction</strong> Operands μops fused μops unfused domain Unit domain p015 p0 p1 p5 p2 p3 p4 Page 93 Latency Reciprocalthroughput
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
Page 41 and 42: Bulldozer FLD m80 8 14 4 fp FBLD m8
Page 43 and 44: Bulldozer MASKMOVQ mm,mm 31 38 37 P
Page 45 and 46: Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
Page 47 and 48: Logic AND/ANDN/OR/XORPS/ PD VAND/AN
Page 49 and 50: Bobcat AMD Bobcat List of instructi
Page 51 and 52: Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
Page 53 and 54: Bobcat Move instructions FLD r 1 2
Page 55 and 56: Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
Page 57 and 58: Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
Page 59 and 60: Intel Pentium Intel Pentium and Pen
Page 61 and 62: Intel Pentium REP MOVS 12+n g) np S
Page 63 and 64: s Intel Pentium May be up to 3 cloc
Page 65 and 66: Pentium II and III PUSHF(D) 3 11 1
Page 67 and 68: Pentium II and III a) Faster under
Page 69 and 70: Pentium II and III PMOVMSKB d) r32,
Page 71 and 72: Pentium M Intel Pentium M, Core Sol
Page 73 and 74: Pentium M DIV IDIV r16 4 3 1 15-24
Page 75 and 76: Pentium M FLD r 1 1 1 FLD m32/64 1
Page 77 and 78: Pentium M MOVNTDQ PACKSSWB/DW m128,
Page 79 and 80: Pentium M MOVUPS/D m128,xmm 8 4 2 2
Page 81 and 82: Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
Page 83 and 84: Merom Move instructions MOV r,r/i 1
Page 85 and 86: Merom ROR ROL m,i/cl 3 2 x x 1 1 1
Page 87 and 88: Merom FLDPI FLDL2E etc. 2 2 2 float
Page 89 and 90: Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91: Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 95 and 96: Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
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Pentium 4 h) Throughput of FP-MUL u
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Prescott MOV r64,i64 2 0 0 1 1 alu1
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Prescott IDIV r8/m8 1 21 76 0 34 1
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Prescott RDPMC (bit 31 = 1) 1 37 10
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Prescott Other FNOP 1 0 1 0 1 0 mov
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Prescott Other EMMS Notes: 10 10 12
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Atom Intel Atom List of instruction
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Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
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Atom NOP (90) 1 ALU0/1 1/2 Long NOP
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Atom PACKSSWB/DW PACKUSWB (x)mm, (x
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Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
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VIA Nano 2000 MOVSX MOVSXD MOVZX r,
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VIA Nano 2000 SETcc m 1 CLC STC CMC
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VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
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VIA Nano 2000 Floating point XMM in
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VIA Nano 2000 REP XCRYPTECB 192 bit
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Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
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Nano 3000 Control transfer instruct
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Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
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PABSB PABSW PABSD PSIGNB PSIGNW PSI
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Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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