4 Instruction tables - Agner Fog

Pentium M
Intel Pentium M, Core Solo and Core Duo
List of instruction timings and μop breakdown
Explanation of column headings:
Operands:
i = immediate data, r = register, mm = 64 bit mmx register, xmm =
128 bit xmm register, sr = segment register, m = memory, m32 =
32-bit memory operand, etc.
μops fused domain: The number of μops at the decode, rename, allocate and retirement
stages in the pipeline. Fused μops count as one.
μops unfused domain: The number of μops for each execution port. Fused μops count as
two.
p0: Port 0: ALU, etc.
p1: Port 1: ALU, jumps
p01:
Instructions that can go to either port 0 or 1, whichever is vacant
first.
p2: Port 2: load data, etc.
p3: Port 3: address generation for store
p4: Port 4: store data
Latency:
This is the delay that the instruction generates in a dependency
chain. (This is not the same as the time spent in the execution
unit. Values may be inaccurate in situations where they cannot be
measured exactly, especially with memory operands). The numbers
are minimum values. Cache misses, misalignment, and exceptions
may increase the clock counts considerably. Floating
point operands are presumed to be normal numbers. Denormal
numbers, NAN's and infinity increase the delays by 50-150 clocks,
except in XMM move, shuffle and Boolean instructions. Floating
point overflow, underflow, denormal or NAN results give a similar
delay.
Reciprocal throughput:
Integer instructions
Instruction Operands μops μops unfused domain Latency
fused
domain p0 p1 p01 p2 p3 p4
Move instructions
The average number of clock cycles per instruction for a series of
independent instructions of the same kind.
MOV r,r/i 1 1 0.5
MOV r,m 1 1 1
MOV m,r 1 1 1 1
MOV m,i 2 1 1 1
MOV r,sr 1 1
MOV m,sr 2 1 1 1
MOV sr,r 8 8 5
MOV sr,m 8 7 1 8
MOVNTI m,r32 2 1 1 2
MOVSX MOVZX r,r 1 1 1 0.5
MOVSX MOVZX r,m 1 1 1
CMOVcc r,r 2 1 1 2 1.5
CMOVcc r,m 2 1 1 1
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Reciprocal
through
put