4 Instruction tables - Agner Fog

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Pentium II and III MULPS xmm,xmm 2 4 2 MULPS xmm,m128 2 2 4 2 MULSS xmm,xmm 1 4 1 MULSS xmm,m32 1 1 4 1 DIVPS xmm,xmm 2 48 34 DIVPS xmm,m128 2 2 48 34 DIVSS xmm,xmm 1 18 17 DIVSS xmm,m32 1 1 18 17 AND(N)PS ORPS XORPS xmm,xmm 2 2 2 AND(N)PS ORPS XORPS xmm,m128 2 2 2 2 MAXPS MINPS xmm,xmm 2 3 2 MAXPS MINPS xmm,m128 2 2 3 2 MAXSS MINSS xmm,xmm 1 3 1 MAXSS MINSS xmm,m32 1 1 3 1 CMPccPS xmm,xmm 2 3 2 CMPccPS xmm,m128 2 2 3 2 CMPccSS xmm,xmm 1 3 1 CMPccSS xmm,m32 1 1 3 1 COMISS UCOMISS xmm,xmm 1 1 1 COMISS UCOMISS xmm,m32 1 1 1 1 SQRTPS xmm,xmm 2 56 56 SQRTPS xmm,m128 2 2 57 56 SQRTSS xmm,xmm 2 30 28 SQRTSS xmm,m32 2 1 31 28 RSQRTPS xmm,xmm 2 2 2 RSQRTPS xmm,m128 2 2 3 2 RSQRTSS xmm,xmm 1 1 1 RSQRTSS xmm,m32 1 1 2 1 RCPPS xmm,xmm 2 2 2 RCPPS xmm,m128 2 2 3 2 RCPSS xmm,xmm 1 1 1 RCPSS xmm,m32 1 1 2 1 SHUFPS xmm,xmm,i 2 1 2 2 SHUFPS xmm,m128,i 2 2 2 2 UNPCKHPS UNPCKLPS xmm,xmm 2 2 3 2 UNPCKHPS UNPCKLPS xmm,m128 2 2 3 2 LDMXCSR m32 11 15 15 STMXCSR m32 6 7 9 FXSAVE m4096 116 62 FXRSTOR m4096 89 68 Page 70
Pentium M Intel Pentium M, Core Solo and Core Duo List of instruction timings and μop breakdown Explanation of column headings: Operands: i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm register, sr = segment register, m = memory, m32 = 32-bit memory operand, etc. μops fused domain: The number of μops at the decode, rename, allocate and retirement stages in the pipeline. Fused μops count as one. μops unfused domain: The number of μops for each execution port. Fused μops count as two. p0: Port 0: ALU, etc. p1: Port 1: ALU, jumps p01: <strong>Instruction</strong>s that can go to either port 0 or 1, whichever is vacant first. p2: Port 2: load data, etc. p3: Port 3: address generation for store p4: Port 4: store data Latency: This is the delay that the instruction generates in a dependency chain. (This is not the same as the time spent in the execution unit. Values may be inaccurate in situations where they cannot be measured exactly, especially with memory operands). The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating point operands are presumed to be normal numbers. Denormal numbers, NAN's and infinity increase the delays by 50-150 clocks, except in XMM move, shuffle and Boolean instructions. Floating point overflow, underflow, denormal or NAN results give a similar delay. Reciprocal throughput: Integer instructions <strong>Instruction</strong> Operands μops μops unfused domain Latency fused domain p0 p1 p01 p2 p3 p4 Move instructions The average number of clock cycles per instruction for a series of independent instructions of the same kind. MOV r,r/i 1 1 0.5 MOV r,m 1 1 1 MOV m,r 1 1 1 1 MOV m,i 2 1 1 1 MOV r,sr 1 1 MOV m,sr 2 1 1 1 MOV sr,r 8 8 5 MOV sr,m 8 7 1 8 MOVNTI m,r32 2 1 1 2 MOVSX MOVZX r,r 1 1 1 0.5 MOVSX MOVZX r,m 1 1 1 CMOVcc r,r 2 1 1 2 1.5 CMOVcc r,m 2 1 1 1 Page 71 Reciprocal through put
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
Page 19 and 20: RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
Page 21 and 22: K8 FNSTSW m16 2 8 FMISC, ALU do. FN
Page 23 and 24: PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
Page 25 and 26: MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
Page 27 and 28: K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
Page 29 and 30: K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
Page 31 and 32: K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
Page 33 and 34: K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
Page 35 and 36: K10 LDMXCSR m 12 12 10 STMXCSR m 3
Page 37 and 38: Bulldozer Integer instructions Inst
Page 39 and 40: Bulldozer TEST m,r 1 0.5 EX01 TEST
Page 41 and 42: Bulldozer FLD m80 8 14 4 fp FBLD m8
Page 43 and 44: Bulldozer MASKMOVQ mm,mm 31 38 37 P
Page 45 and 46: Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
Page 47 and 48: Logic AND/ANDN/OR/XORPS/ PD VAND/AN
Page 49 and 50: Bobcat AMD Bobcat List of instructi
Page 51 and 52: Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
Page 53 and 54: Bobcat Move instructions FLD r 1 2
Page 55 and 56: Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
Page 57 and 58: Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
Page 59 and 60: Intel Pentium Intel Pentium and Pen
Page 61 and 62: Intel Pentium REP MOVS 12+n g) np S
Page 63 and 64: s Intel Pentium May be up to 3 cloc
Page 65 and 66: Pentium II and III PUSHF(D) 3 11 1
Page 67 and 68: Pentium II and III a) Faster under
Page 69: Pentium II and III PMOVMSKB d) r32,
Page 73 and 74: Pentium M DIV IDIV r16 4 3 1 15-24
Page 75 and 76: Pentium M FLD r 1 1 1 FLD m32/64 1
Page 77 and 78: Pentium M MOVNTDQ PACKSSWB/DW m128,
Page 79 and 80: Pentium M MOVUPS/D m128,xmm 8 4 2 2
Page 81 and 82: Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
Page 83 and 84: Merom Move instructions MOV r,r/i 1
Page 85 and 86: Merom ROR ROL m,i/cl 3 2 x x 1 1 1
Page 87 and 88: Merom FLDPI FLDL2E etc. 2 2 2 float
Page 89 and 90: Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91 and 92: Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 93 and 94: Wolfdale Intel Core 2 (Wolfdale, 45
Page 95 and 96: Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
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Sandy Bridge INC DEC NEG NOT r 1 1
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Sandy Bridge CALL m 3 2 1 2 1 2 RET
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Sandy Bridge FYL2XP1 464 464 726 FP
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Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
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Sandy Bridge MOVMSKPS/D r32,x 1 1 1
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Sandy Bridge ADDSS/D SUBSS/D x,x 1
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Pentium 4 Intel Pentium 4 List of i
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Pentium 4 SFENCE 4 2 40 sse LFENCE
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Pentium 4 RETF i 4 33 11 0 86 IRET
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Pentium 4 Math FSQRT 1 0 43 0 43 1
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Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
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Pentium 4 h) Throughput of FP-MUL u
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Prescott MOV r64,i64 2 0 0 1 1 alu1
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Prescott IDIV r8/m8 1 21 76 0 34 1
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Prescott RDPMC (bit 31 = 1) 1 37 10
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Prescott Other FNOP 1 0 1 0 1 0 mov
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Prescott Other EMMS Notes: 10 10 12
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Atom Intel Atom List of instruction
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Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
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Atom NOP (90) 1 ALU0/1 1/2 Long NOP
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Atom PACKSSWB/DW PACKUSWB (x)mm, (x
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Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
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VIA Nano 2000 MOVSX MOVSXD MOVZX r,
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VIA Nano 2000 SETcc m 1 CLC STC CMC
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VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
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VIA Nano 2000 Floating point XMM in
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VIA Nano 2000 REP XCRYPTECB 192 bit
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Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
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Nano 3000 Control transfer instruct
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Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
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PABSB PABSW PABSD PSIGNB PSIGNW PSI
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Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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