4 Instruction tables - Agner Fog

Pentium II and III
Intel Pentium II and Pentium III
List of instruction timings and μop breakdown
Explanation of column headings:
Operands:
i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm
register, sr = segment register, m = memory, m32 = 32-bit memory operand, etc.
μops: The number of μops that the instruction generates for each execution port.
p0: Port 0: ALU, etc.
p1: Port 1: ALU, jumps
p01: Instructions that can go to either port 0 or 1, whichever is vacant first.
p2: Port 2: load data, etc.
p3: Port 3: address generation for store
p4: Port 4: store data
Latency:
This is the delay that the instruction generates in a dependency chain. (This is
not the same as the time spent in the execution unit. Values may be inaccurate
in situations where they cannot be measured exactly, especially with memory
operands). The numbers are minimum values. Cache misses, misalignment, and
exceptions may increase the clock counts considerably. Floating point operands
are presumed to be normal numbers. Denormal numbers, NAN's and infinity increase
the delays by 50-150 clocks, except in XMM move, shuffle and Boolean
instructions. Floating point overflow, underflow, denormal or NAN results give a
similar delay.
Reciprocal throughput:
The average number of clock cycles per instruction for a series of independent
instructions of the same kind.
Integer instructions (Pentium Pro, Pentium II and Pentium III)
Instruction Operands μops Latency
p0 p1 p01 p2 p3 p4
MOV r,r/i 1
MOV r,m 1
MOV m,r/i 1 1
MOV r,sr 1
MOV m,sr 1 1 1
MOV sr,r 8 5
MOV sr,m 7 1 8
MOVSX MOVZX r,r 1
MOVSX MOVZX r,m 1
CMOVcc r,r 1 1
CMOVcc r,m 1 1 1
XCHG r,r 3
XCHG r,m 4 1 1 1 high b)
XLAT 1 1
PUSH r/i 1 1 1
POP r 1 1
POP (E)SP 2 1
PUSH m 1 1 1 1
POP m 5 1 1 1
PUSH sr 2 1 1
POP sr 8 1
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Reciprocal
throughput