4 Instruction tables - Agner Fog

Intel Pentium
REP MOVS 12+n g) np
SCAS 4 np
REP(N)E SCAS 9+4*n g) np
CMPS 5 np
REP(N)E CMPS 8+4*n g) np
BSWAP r 1 a) np
CPUID 13-16 a) np
RDTSC 6-13 a) j) np
Notes:
a
b versions with FS and GS have a 0FH prefix. see note a.
c versions with SS, FS, and GS have a 0FH prefix. see note a.
d
versions with two operands and no immediate have a 0FH prefix,
see note a.
e high values are for mispredicted jumps/branches.
f only pairable if register is AL, AX or EAX.
g
add one clock cycle for decoding the repeat prefix unless preceded
by a multi-cycle instruction (such as CLD).
h pairs as if it were writing to the accumulator.
i 9 if SP divisible by 4 (imperfect pairing).
j
on P1: 6 in privileged or real mode; 11 in non-privileged; error in
virtual mode. On PMMX: 8 and 13 clocks respectively.
Floating point instructions (Pentium and Pentium MMX)
Explanation of column headings
Operands r = register, m = memory, m32 = 32-bit memory operand, etc.
Clock cycles
The numbers are minimum values. Cache misses, misalignment,
denormal operands, and exceptions may increase the clock
counts considerably.
Pairability + = pairable with FXCH, np = not pairable with FXCH.
i-ov
Overlap with integer instructions. i-ov = 4 means that the last four
clock cycles can overlap with subsequent integer instructions.
fp-ov
This instruction has a 0FH prefix which takes one clock cycle extra
to decode on a P1 unless preceded by a multi-cycle instruction.
Overlap with floating point instructions. fp-ov = 2 means that the
last two clock cycles can overlap with subsequent floating point
instructions. (WAIT is considered a floating point instruction here)
Instruction Operand Clock cycles Pairability i-ov fp-ov
FLD r/m32/m64 1 0 0 0
FLD m80 3 np 0 0
FBLD m80 48-58 np 0 0
FST(P) r 1 np 0 0
FST(P) m32/m64 2 m) np 0 0
FST(P) m80 3 m) np 0 0
FBSTP m80 148-154 np 0 0
FILD m 3 np 2 2
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