4 Instruction tables - Agner Fog

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Microprocessors tested Microprocessor versions tested The tables in this manual are based on testing of the following microprocessors Family Model Microarchitecture number number Processor name Code name (hex) (hex) Comment AMD K7 Athlon 6 6 Step. 2, rev. A5 AMD K8 Opteron F 5 Stepping A AMD K10 Opteron 10 2 2350, step. 1 AMD Bulldozer Bulldozer, Zambezi 15 1 FX-6100, step 2 AMD Bobcat Bobcat 14 1 E350, step. 0 Intel Pentium 5 2 Intel Pentium MMX P5 5 4 Stepping 4 Intel Pentium II P6 6 6 Intel Pentium III P6 6 7 Intel Pentium 4 Netburst F 2 Stepping 4, rev. B0 Intel Pentium 4 EM64T Netburst, Prescott F 4 Xeon. Stepping 1 Intel Pentium M Dothan 6 D Stepping 6, rev. B1 Intel Core Duo Yonah 6 E Not fully tested Intel Core 2 (65 nm) Merom 6 F T5500, Step. 6, rev. B2 Intel Core 2 (45 nm) Wolfdale 6 17 E8400, Step. 6 Intel Core i7 Nehalem 6 1A i7-920, Step. 5, rev. D0 Intel Core i5 Sandy Bridge 6 2A i5-2500, Step 7 Intel Atom 330 Diamondville 6 1C Step. 2 VIA Nano L2200 6 F Step. 2 VIA Nano L3050 Isaiah 6 F Step. 8 (prerel. sample) Page 6
AMD K7 AMD K7 List of instruction timings and macro-operation breakdown Explanation of column headings: Instruction: Instruction name. cc means any condition code. For example, Jcc can be JB, JNE, etc. Operands: i = immediate constant, r = any register, r32 = 32-bit register, etc., mm = 64 bit mmx register, xmm = 128 bit xmm register, sr = segment register, m = any memory operand including indirect operands, m64 means 64-bit memory operand, etc. Ops: Latency: Reciprocal throughput: Execution unit: Number of macro-operations issued from instruction decoder to schedulers. Instructions with more than 2 macro-operations use microcode. This is the delay that the instruction generates in a dependency chain. The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating point operands are presumed to be normal numbers. Denormal numbers, NAN's, infinity and exceptions increase the delays. The latency listed does not include the memory operand where the operand is listed as register or memory (r/m). This is also called issue latency. This value indicates the average number of clock cycles from the execution of an instruction begins to a subsequent independent instruction of the same kind can begin to execute. A value of 1/3 indicates that the execution units can handle 3 instructions per clock cycle in one thread. However, the throughput may be limited by other bottlenecks in the pipeline. Indicates which execution unit is used for the macro-operations. ALU means any of the three integer ALU's. ALU0_1 means that ALU0 and ALU1 are both used. AGU means any of the three integer address generation units. FADD means floating point adder unit. FMUL means floating point multiplier unit. FMISC means floating point store and miscellaneous unit. FA/M means FADD or FMUL is used. FANY means any of the three floating point units can be used. Two macro-operations can execute simultaneously if they go to different execution units. Integer instructions Instruction Operands Ops Latency Reciprocal Execution Notes Move instructions throughput unit MOV r,r 1 1 1/3 ALU MOV r,i 1 1 1/3 ALU Any addr. mode. Add 1 clk if code segment base ≠ MOV r8,m8 1 4 1/2 ALU, AGU 0 MOV r16,m16 1 4 1/2 ALU, AGU do. MOV r32,m32 1 3 1/2 AGU do. MOV m8,r8H 1 8 1/2 AGU AH, BH, CH, DH Any other 8-bit MOV m8,r8L 1 2 1/2 AGU register Any addressing MOV m16/32,r 1 2 1/2 AGU mode MOV m,i 1 2 1/2 AGU MOV r,sr 1 2 1 Page 7
Page 1 and 2: Introduction 4 Instruction tables L
Page 3 and 4: Definition of terms Operands Latenc
Page 5: Definition of terms It is not possi
Page 9 and 10: AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
Page 11 and 12: AMD K7 Other NOP (90) 1 0 1/3 ALU L
Page 13 and 14: AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
Page 15 and 16: AMD K7 Integer instructions PAVGUSB
Page 17 and 18: MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
Page 19 and 20: RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
Page 21 and 22: K8 FNSTSW m16 2 8 FMISC, ALU do. FN
Page 23 and 24: PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
Page 25 and 26: MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
Page 27 and 28: K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
Page 29 and 30: K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
Page 31 and 32: K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
Page 33 and 34: K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
Page 35 and 36: K10 LDMXCSR m 12 12 10 STMXCSR m 3
Page 37 and 38: Bulldozer Integer instructions Inst
Page 39 and 40: Bulldozer TEST m,r 1 0.5 EX01 TEST
Page 41 and 42: Bulldozer FLD m80 8 14 4 fp FBLD m8
Page 43 and 44: Bulldozer MASKMOVQ mm,mm 31 38 37 P
Page 45 and 46: Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
Page 47 and 48: Logic AND/ANDN/OR/XORPS/ PD VAND/AN
Page 49 and 50: Bobcat AMD Bobcat List of instructi
Page 51 and 52: Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
Page 53 and 54: Bobcat Move instructions FLD r 1 2
Page 55 and 56: Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
Page 57 and 58:
Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
Page 59 and 60:
Intel Pentium Intel Pentium and Pen
Page 61 and 62:
Intel Pentium REP MOVS 12+n g) np S
Page 63 and 64:
s Intel Pentium May be up to 3 cloc
Page 65 and 66:
Pentium II and III PUSHF(D) 3 11 1
Page 67 and 68:
Pentium II and III a) Faster under
Page 69 and 70:
Pentium II and III PMOVMSKB d) r32,
Page 71 and 72:
Pentium M Intel Pentium M, Core Sol
Page 73 and 74:
Pentium M DIV IDIV r16 4 3 1 15-24
Page 75 and 76:
Pentium M FLD r 1 1 1 FLD m32/64 1
Page 77 and 78:
Pentium M MOVNTDQ PACKSSWB/DW m128,
Page 79 and 80:
Pentium M MOVUPS/D m128,xmm 8 4 2 2
Page 81 and 82:
Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
Page 83 and 84:
Merom Move instructions MOV r,r/i 1
Page 85 and 86:
Merom ROR ROL m,i/cl 3 2 x x 1 1 1
Page 87 and 88:
Merom FLDPI FLDL2E etc. 2 2 2 float
Page 89 and 90:
Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91 and 92:
Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 93 and 94:
Wolfdale Intel Core 2 (Wolfdale, 45
Page 95 and 96:
Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98:
Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100:
Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102:
Wolfdale Arithmetic instructions PA
Page 103 and 104:
Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106:
Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108:
Latency: Reciprocal throughput: Neh
Page 109 and 110:
Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112:
Nehalem Floating point x87 instruct
Page 113 and 114:
Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116:
Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118:
Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120:
Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122:
Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124:
Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126:
Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128:
Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130:
Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132:
Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134:
Pentium 4 Intel Pentium 4 List of i
Page 135 and 136:
Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138:
Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140:
Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142:
Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 143 and 144:
Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146:
Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148:
Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150:
Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152:
Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154:
Prescott Other EMMS Notes: 10 10 12
Page 155 and 156:
Atom Intel Atom List of instruction
Page 157 and 158:
Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160:
Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162:
Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164:
Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166:
VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168:
VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170:
VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172:
VIA Nano 2000 Floating point XMM in
Page 173 and 174:
VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176:
Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178:
Nano 3000 Control transfer instruct
Page 179 and 180:
Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182:
PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183:
Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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