4 Instruction tables - Agner Fog
4 Instruction tables - Agner Fog
4 Instruction tables - Agner Fog
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K10<br />
AAA, AAS 9 5 5 ALU<br />
DAA 12 6 6 ALU<br />
DAS 16 7 7 ALU<br />
AAD 4 5 5 ALU0<br />
AAM 30 13 13 ALU<br />
MUL, IMUL r8/m8 1 3 1 ALU0<br />
MUL, IMUL r16/m16 3 3 2 ALU0_1 latency ax=3, dx=4<br />
MUL, IMUL r32/m32 2 3 1 ALU0_1<br />
MUL, IMUL r64/m64 2 4 2 ALU0_1 latency rax=4, rdx=5<br />
IMUL r16,r16/m16 1 3 1 ALU0<br />
IMUL r32,r32/m32 1 3 1 ALU0<br />
IMUL r64,r64/m64 1 4 2 ALU0_1<br />
IMUL r16,(r16),i 2 4 1 ALU0<br />
IMUL r32,(r32),i 1 3 1 ALU0<br />
IMUL r64,(r64),i 1 4 2 ALU0<br />
IMUL r16,m16,i 3 2 ALU0<br />
IMUL r32,m32,i 3 2 ALU0<br />
IMUL r64,m64,i 3 2 ALU0_1<br />
DIV r8/m8 17 17 ALU<br />
IDIV r8 19 19 ALU<br />
IDIV m8 22 22 ALU<br />
DIV r16/m16 15-30 15-30 ALU<br />
DIV r32/m32 15-46 15-46 ALU<br />
DIV r64/m64 15-78 15-78 ALU<br />
IDIV r16/m16 24-39 24-39 ALU<br />
IDIV r32/m32 24-55 24-55 ALU<br />
IDIV r64/m64 24-87 24-87 ALU<br />
CBW, CWDE, CDQE 1 1 1/3 ALU<br />
CWD, CDQ, CQO 1 1 1/3 ALU<br />
Logic instructions<br />
AND, OR, XOR r,r 1 1 1/3 ALU<br />
AND, OR, XOR r,m 1 1/2 ALU, AGU<br />
AND, OR, XOR m,r 1 4 1 ALU, AGU<br />
TEST r,r 1 1 1/3 ALU<br />
TEST r,m 1 1/2 ALU, AGU<br />
NOT r 1 1 1/3 ALU<br />
NOT m 1 7 1 ALU, AGU<br />
SHL, SHR, SAR r,i/CL 1 1 1/3 ALU<br />
ROL, ROR r,i/CL 1 1 1/3 ALU<br />
RCL, RCR r,1 1 1 1 ALU<br />
RCL r,i 9 3 3 ALU<br />
RCR r,i 7 3 3 ALU<br />
RCL r,CL 9 4 4 ALU<br />
RCR r,CL 7 3 3 ALU<br />
SHL,SHR,SAR,ROL,ROR m,i /CL 1 7 1 ALU, AGU<br />
RCL, RCR m,1 1 7 1 ALU, AGU<br />
RCL m,i 10 7 5 ALU, AGU<br />
RCR m,i 9 7 6 ALU, AGU<br />
RCL m,CL 9 8 6 ALU, AGU<br />
Page 28<br />
Depends on number<br />
of significant bits in<br />
absolute value of<br />
dividend. See AMD<br />
software optimization<br />
guide.
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