4 Instruction tables - Agner Fog

K10
AMD K10
List of instruction timings and macro-operation breakdown
Explanation of column headings:
Instruction:
Instruction name. cc means any condition code. For example, Jcc can be JB,
JNE, etc.
Operands:
i = immediate constant, r = any register, r32 = 32-bit register, etc., mm = 64 bit
mmx register, xmm = 128 bit xmm register, sr = segment register, m = any
memory operand including indirect operands, m64 means 64-bit memory operand,
etc.
Ops:
Latency:
Reciprocal throughput:
Execution unit:
Number of macro-operations issued from instruction decoder to schedulers. Instructions
with more than 2 macro-operations use microcode.
This is the delay that the instruction generates in a dependency chain. The numbers
are minimum values. Cache misses, misalignment, and exceptions may increase
the clock counts considerably. Floating point operands are presumed to
be normal numbers. Denormal numbers, NAN's, infinity and exceptions increase
the delays. The latency listed does not include the memory operand where the
operand is listed as register or memory (r/m).
This is also called issue latency. This value indicates the average number of clock
cycles from the execution of an instruction begins to a subsequent independent
instruction of the same kind can begin to execute. A value of 1/3 indicates that the
execution units can handle 3 instructions per clock cycle in one thread. However,
the throughput may be limited by other bottlenecks in the pipeline.
Indicates which execution unit is used for the macro-operations. ALU means any
of the three integer ALU's. ALU0_1 means that ALU0 and ALU1 are both used.
AGU means any of the three integer address generation units. FADD means floating
point adder unit. FMUL means floating point multiplier unit. FMISC means
floating point store and miscellaneous unit. FA/M means FADD or FMUL is used.
FANY means any of the three floating point units can be used. Two macro-operations
can execute simultaneously if they go to different execution units.
Integer instructions
Instruction
Move instructions
Operands Ops Latency Reciprocal
throughput
Execution unit Notes
MOV r,r 1 1 1/3 ALU
MOV r,i 1 1 1/3 ALU
MOV r8,m8 1 4 1/2 ALU, AGU Any addressing
MOV
MOV
MOV
r16,m16
r32,m32
r64,m64
1
1
1
4
3
3
1/2
1/2
1/2
ALU, AGU
AGU
AGU
mode. Add 1 clock if
code segment base
≠ 0
MOV m8,r8H 1 8 1/2 AGU AH, BH, CH, DH
Any other 8-bit
MOV m8,r8L 1 3 1/2 AGU register
MOV m16/32/64,r 1 3 1/2 AGU Any addressing
MOV m,i 1 3 1/2 AGU mode
MOV m64,i32 1 3 1/2 AGU
MOV r,sr 1 3-4 1/2
MOV sr,r/m 6 8-26 8 from AMD manual
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