4 Instruction tables - Agner Fog

Nano 3000
VIA Nano 3000 series
List of instruction timings and μop breakdown
Explanation of column headings:
Operands:
i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm
register, (x)mm = mmx or xmm register, sr = segment register, m = memory,
m32 = 32-bit memory operand, etc.
μops:
Port:
Latency:
The number of micro-operations from the decoder or ROM. Note that the VIA
Nano 3000 processor has no reliable performance monitor counter for μops.
Therefore the number of μops cannot be determined except in simple cases.
Tells which execution port or unit is used. Instructions that use the same port
cannot execute simultaneously.
I1: Integer add, Boolean, shift, etc.
I2: Integer add, Boolean, move, jump.
I12: Can use either I1 or I2, whichever is vacant first.
MA: Multiply, divide and square root on all operand types.
MB: Various Integer and floating point SIMD operations.
MBfadd: Floating point addition subunit under MB.
SA: Memory store address.
ST: Memory store.
LD: Memory load.
This is the delay that the instruction generates in a dependency chain. The
numbers are minimum values. Cache misses, misalignment, and exceptions
may increase the clock counts considerably. Floating point operands are presumed
to be normal numbers. Denormal numbers, NAN's and infinity increase
the delays very much, except in XMM move, shuffle and Boolean instructions.
Floating point overflow, underflow, denormal or NAN results give a similar delay.
Note: There is an additional latency for moving data from one unit or subunit to
another. A table of these latencies is given in manual 3: "The microarchitecture
of Intel, AMD and VIA CPUs". These additional latencies are not included in the
listings below where the source and destination operands are of the same type.
Reciprocal throughput: The average number of clock cycles per instruction for a series of independent
instructions of the same kind in the same thread.
Integer instructions
Operands μops Port Latency Reciprocalthruoghput
Remarks
Move instructions
MOV r,r 1 I2 1 1
MOV r,i 1 I12 1 1/2
MOV r,m 1 LD 2 1
Latency 4 on pointer
register
MOV m,r 1 SA, ST 2 1.5
MOV m,i 1 SA, ST 1.5
MOV r,sr I12 1/2
MOV m,sr 1.5
MOV sr,r 20 20
MOV sr,m 20 20
MOVNTI m,r SA, ST 2 1.5
Page 174