4 Instruction tables - Agner Fog

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VIA Nano 2000 ADDPD SUBPD xmm,xmm 1 MBfadd 2-3 1 ADDSUBPS xmm,xmm 1 MBfadd 2-3 1 ADDSUBPD xmm,xmm 1 MBfadd 2-3 1 HADDPS HSUBPS xmm,xmm MBfadd 5 3 HADDPD HSUBPD xmm,xmm MBfadd 5 3 MULSS xmm,xmm 1 MA 3 1 MULSD xmm,xmm 1 MA 4 2 MULPS xmm,xmm MA 3 1 MULPD xmm,xmm MA 4 2 DIVSS xmm,xmm MA 15-22 15-22 DIVSD xmm,xmm MA 15-36 15-36 DIVPS xmm,xmm MA 42-82 42-82 DIVPD xmm,xmm MA 24-70 24-70 RCPSS xmm,xmm 5 5 RCPPS xmm,xmm 14 11 CMPccSS/D xmm,xmm 1 MBfadd 2 1 CMPccPS/D xmm,xmm 1 MBfadd 2 1 COMISS/D UCOMISS/D xmm,xmm 3 1 MAXSS/D MINSS/D xmm,xmm 1 MBfadd 2 1 MAXPS/D MINPS/D xmm,xmm 1 MBfadd 2 1 Math SQRTSS xmm,xmm MA 33 33 SQRTPS xmm,xmm MA 126 126 SQRTSD xmm,xmm MA 62 62 SQRTPD xmm,xmm MA 122 122 RSQRTSS xmm,xmm 5 5 RSQRTPS xmm,xmm 14 11 Logic ANDPS/D xmm,xmm 1 MB 1 1 ANDNPS/D xmm,xmm 1 MB 1 1 ORPS/D xmm,xmm 1 MB 1 1 XORPS/D xmm,xmm 1 MB 1 1 Other LDMXCSR m32 45 29 STMXCSR m32 13 13 FXSAVE m4096 208 208 FXRSTOR m4096 232 232 VIA-specific instructions <strong>Instruction</strong> Conditions Clock cycles, approximately XSTORE Data available 160-400 clock giving 8 bytes XSTORE No data available 50-80 clock giving 0 bytes REP XSTORE Quality factor = 0 4800 clock per 8 bytes REP XSTORE Quality factor > 0 19200 clock per 8 bytes REP XCRYPTECB 128 bits key 44 clock per 16 bytes Page 172
VIA Nano 2000 REP XCRYPTECB 192 bits key 46 clock per 16 bytes REP XCRYPTECB 256 bits key 48 clock per 16 bytes REP XCRYPTCBC 128 bits key 54 clock per 16 bytes REP XCRYPTCBC 192 bits key 59 clock per 16 bytes REP XCRYPTCBC 256 bits key 63 clock per 16 bytes REP XCRYPTCTR 128 bits key 43 clock per 16 bytes REP XCRYPTCTR 192 bits key 46 clock per 16 bytes REP XCRYPTCTR 256 bits key 48 clock per 16 bytes REP XCRYPTCFB 128 bits key 54 clock per 16 bytes REP XCRYPTCFB 192 bits key 59 clock per 16 bytes REP XCRYPTCFB 256 bits key 63 clock per 16 bytes REP XCRYPTOFB 128 bits key 54 clock per 16 bytes REP XCRYPTOFB 192 bits key 59 clock per 16 bytes REP XCRYPTOFB 256 bits key 63 clock per 16 bytes REP XSHA1 3 clock per byte REP XSHA256 4 clock per byte Page 173
Page 1 and 2:
Introduction 4 Instruction tables L
Page 3 and 4:
Definition of terms Operands Latenc
Page 5 and 6:
Definition of terms It is not possi
Page 7 and 8:
AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
Page 29 and 30:
K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
Page 31 and 32:
K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
Page 33 and 34:
K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
Page 37 and 38:
Bulldozer Integer instructions Inst
Page 39 and 40:
Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
Page 47 and 48:
Logic AND/ANDN/OR/XORPS/ PD VAND/AN
Page 49 and 50:
Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
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Merom ROR ROL m,i/cl 3 2 x x 1 1 1
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Merom FLDPI FLDL2E etc. 2 2 2 float
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Merom PALIGNR h) xmm,m128,i 2 2 x x
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Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
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Wolfdale Intel Core 2 (Wolfdale, 45
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Wolfdale ADC SBB r,m 2 2 x x x 1 2
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Wolfdale LODS 3 2 1 1 REP LODS 4+7n
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Wolfdale Other FNOP 1 1 1 float 1 W
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Wolfdale Arithmetic instructions PA
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Wolfdale SHUFPS xmm,m128,i 2 1 1 1
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Wolfdale DPPD j) xmm,m128,i 4 4 x x
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Latency: Reciprocal throughput: Neh
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Nehalem CBW CWDE CDQE 1 1 x x x int
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Nehalem Floating point x87 instruct
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Nehalem MOVNTDQA j) PACKSSWB/DW PAC
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Nehalem PHMINPOSUW j) PABSB PABSW P
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Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
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Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 143 and 144: Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150: Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166: VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171: VIA Nano 2000 Floating point XMM in
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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