4 Instruction tables - Agner Fog

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VIA Nano 2000 VIA Nano 2000 series List of instruction timings and μop breakdown Explanation of column headings: Operands: i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm register, (x)mm = mmx or xmm register, sr = segment register, m = memory, m32 = 32-bit memory operand, etc. μops: Port: Latency: The number of micro-operations from the decoder or ROM. Note that the VIA Nano 2000 processor has no reliable performance monitor counter for μops. Therefore the number of μops cannot be determined except in simple cases. Tells which execution port or unit is used. <strong>Instruction</strong>s that use the same port cannot execute simultaneously. I1: Integer add, Boolean, shift, etc. I2: Integer add, Boolean, move, jump. I12: Can use either I1 or I2, whichever is vacant first. MA: Multiply, divide and square root on all operand types. MB: Various Integer and floating point SIMD operations. MBfadd: Floating point addition subunit under MB. SA: Memory store address. ST: Memory store. LD: Memory load. This is the delay that the instruction generates in a dependency chain. The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating point operands are presumed to be normal numbers. Denormal numbers, NAN's and infinity increase the delays very much, except in XMM move, shuffle and Boolean instructions. Floating point overflow, underflow, denormal or NAN results give a similar delay. Note: There is an additional latency for moving data from one unit or subunit to another. A table of these latencies is given in manual 3: "The microarchitecture of Intel, AMD and VIA CPUs". These additional latencies are not included in the listings below where the source and destination operands are of the same type. Reciprocal throughput: The average number of clock cycles per instruction for a series of independent instructions of the same kind in the same thread. Integer instructions Operands μops Port Latency Reciprocalthruoghput Remarks Move instructions MOV r,r 1 I2 1 1 MOV r,i 1 I2 1 1 MOV r,m 1 LD 2 1 Latency 4 on pointer register MOV m,r 1 SA, ST 2 1.5 MOV m,i 1 SA, ST 1.5 MOV r,sr 1 MOV m,sr 2 MOV sr,r 20 20 MOV sr,m 20 20 MOVNTI m,r SA, ST 2 1.5 Page 164
VIA Nano 2000 MOVSX MOVSXD MOVZX r,r 1 I2 1 1 MOVSX MOVSXD r,m 2 LD, I2 3 1 MOVZX r,m 1 LD 2 1 CMOVcc r,r 2 I1, I2 2 1 CMOVcc r,m LD, I1 5 2 XCHG r,r 3 I2 3 3 XCHG r,m 20 20 Implicit lock XLAT m 6 PUSH r SA, ST 1-2 PUSH i SA, ST 1-2 PUSH m Ld, SA, ST 2 PUSH sr 17 PUSHF(D/Q) 8 8 PUSHA(D) 15 Not in x64 mode POP r LD 1.25 POP (E/R)SP 4 POP m 5 POP sr 20 POPF(D/Q) 9 9 POPA(D) 12 Not in x64 mode LAHF 1 I1 1 1 SAHF 1 I1 1 1 SALC 9 6 Not in x64 mode LEA r,m 1 SA 1 1 3 clock latency on input register BSWAP LDS LES LFS LGS LSS r 1 I2 1 1 m 30 30 PREFETCHNTA m LD 1-2 PREFETCHT0/1/2 m LD 1-2 LFENCE 14 MFENCE 14 SFENCE 14 Arithmetic instructions ADD SUB r,r/i 1 I12 1 1/2 ADD SUB r,m 2 LD I12 1 ADD SUB m,r/i 3 LD I12 SA ST 5 2 ADC SBB r,r/i 1 I1 1 1 ADC SBB r,m 2 LD I1 1 ADC SBB m,r/i 3 LD I1 SA ST 5 2 CMP r,r/i 1 I12 1 1/2 CMP m,r/i 2 LD I12 1 INC DEC NEG NOT r 1 I12 1 1/2 INC DEC NEG NOT m 3 LD I12 SA ST 5 AAA 37 Not in x64 mode AAS 37 Not in x64 mode DAA 22 Not in x64 mode DAS 24 Not in x64 mode Page 165
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
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Logic AND/ANDN/OR/XORPS/ PD VAND/AN
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Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
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Merom ROR ROL m,i/cl 3 2 x x 1 1 1
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Merom FLDPI FLDL2E etc. 2 2 2 float
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Merom PALIGNR h) xmm,m128,i 2 2 x x
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Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
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Wolfdale Intel Core 2 (Wolfdale, 45
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Wolfdale ADC SBB r,m 2 2 x x x 1 2
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Wolfdale LODS 3 2 1 1 REP LODS 4+7n
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Wolfdale Other FNOP 1 1 1 float 1 W
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Wolfdale Arithmetic instructions PA
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Wolfdale SHUFPS xmm,m128,i 2 1 1 1
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Wolfdale DPPD j) xmm,m128,i 4 4 x x
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Latency: Reciprocal throughput: Neh
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Nehalem CBW CWDE CDQE 1 1 x x x int
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Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 143 and 144: Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150: Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172: VIA Nano 2000 Floating point XMM in
Page 173 and 174: VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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