4 Instruction tables - Agner Fog

Atom
CMOVcc r,m 1 3
XCHG r,r 3 6 6
XCHG r,m 4 6 6 Implicit lock
XLAT 3 6 6
PUSH r 1 np 1 1
PUSH i 1 np 1
PUSH m 2 5
PUSH sr 3 6
PUSHF(D/Q) 14 12
PUSHA(D) 9 11 Not in x64 mode
POP r 1 np 1 1
POP (E/R)SP 1 np 1 1
POP m 3 6
POP sr 7 31
POPF(D/Q) 19 28
POPA(D) 16 12 Not in x64 mode
LAHF 1 ALU0+1 2 2
SAHF 1 ALU0/1 1 1/2
SALC 2 7 5 Not in x64 mode
LEA r,m 1 AGU1 1-4 1
BSWAP r 1 ALU0 1 1
LDS LES LFS LGS LSS m 10 30 30
PREFETCHNTA m 1 Mem 1
PREFETCHT0/1/2 m 1 Mem 1
LFENCE 1 1/2
MFENCE 1 1
SFENCE 1 1
Arithmetic instructions
ADD SUB r,r/i 1 ALU0/1 1 1/2
ADD SUB r,m 1 ALU0/1, Mem 1
ADD SUB m,r/i 1 2 1
ADC SBB r,r/i 1 2 2
ADC SBB r,m 1 2 2
ADC SBB m,r/i 1 2 2
CMP r,r/i 1 ALU0/1 1 1/2
CMP m,r/i 1 1
INC DEC NEG NOT r 1 ALU0/1 1 1/2
INC DEC NEG NOT m 1 1
AAA 13 16 Not in x64 mode
AAS 13 12 Not in x64 mode
DAA 20 20 Not in x64 mode
DAS 21 25 Not in x64 mode
AAD 4 7 Not in x64 mode
AAM 10 24 Not in x64 mode
MUL IMUL r8 3 ALU0, Mul 7 7
MUL IMUL r16 4 ALU0, Mul 6 6
MUL IMUL r32 3 ALU0, Mul 6 6
MUL IMUL r64 8 ALU0, Mul 14 14
Page 156
4 clock latency
on input register