4 Instruction tables - Agner Fog

Prescott
RDPMC (bit 31 = 1) 1 37 100 p5
RDPMC (bit 31 = 0) 4 154 240 p5
MONITOR (sse3)
MWAIT
Notes:
(sse3)
a) Add 1 μop if source is a memory operand.
b) Uses an extra μop (port 3) if SIB byte used.
c)
Add 1 μop if source or destination, but not both, is a high 8-bit register (AH, BH,
CH, DH).
d) Has (false) dependence on the flags in most cases.
e) Not available on PMMX
l)
Move accumulator to/from memory with 64 bit absolute address (opcode A0 -
A3).
m) Not available in 64 bit mode.
n) Not available in 64 bit mode on some processors.
o)
MOVSX uses an extra μop if the destination register is smaller than the biggest
register size available. Use a 32 bit destination register in 16 bit and 32 bit
mode, and a 64 bit destination register in 64 bit mode for optimal performance.
p)
LEA with a direct memory operand has 1 μop and a reciprocal throughput of
0.25. This also applies if there is a RIP-relative address in 64-bit mode. A signextended
32-bit direct memory operand in 64-bit mode without RIP-relative address
takes 2 μops because of the SIB byte. The throughput is 1 in this case.
You may use a MOV instead.
q)
Floating point x87 instructions
Instruction Operands
These values are measured in 32-bit mode. In 16-bit real mode there is 1 microcode
μop and a reciprocal throughput of 17.
μops
Microcode
Latency
Page 149
Additional latency
Reciprocal throughput
Move instructions
FLD r 1 0 7 0 1 0 mov 87
FLD m32/64 1 0 0 1 2 load 87
FLD m80 3 3 8 2 load 87
FBLD m80 3 74 90 2 load 87
FST(P) r 1 0 7 0 1 0 mov 87
FST(P) m32/64 2 0 7 2 0 store 87
FSTP m80 3 6 10 0 store 87
FBSTP m80 3 311 400 0 store 87
FXCH r 1 0 0 0 1 0 mov 87
FILD m16 3 2 8 2 load 87
FILD m32/64 2 0 2 2 load 87
FIST(P) m 3 0 2.5 0 store 87
FISTTP m 3 0 2.5 0 store sse3
FLDZ 1 0 2 0 mov 87
Port
Execution unit
Subunit
Instruction set
Notes