4 Instruction tables - Agner Fog

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Prescott SHRD r64,r64,cl 3 8 12 0 1 alu1 x64 SHLD, SHRD m,r,i 3 8 20 0 10 1 alu1 386 SHLD, SHRD m,r,CL 2 8 20 0 10 1 alu1 386 BT r,i 1 0 8 0 8 1 alu1 386 d BT r,r 2 0 9 0 9 1 alu1 386 d BT m,i 3 0 8 0 8 1 alu1 386 d BT m,r 2 7 10 0 10 1 alu1 386 d BTR, BTS, BTC r,i 1 0 8 0 8 1 alu1 386 BTR, BTS, BTC r,r 2 0 9 0 9 1 alu1 386 BTR, BTS, BTC m,i 3 6 28 0 10 1 alu1 386 BTR, BTS, BTC m,r 2 10 14 0 14 1 alu1 386 BSF, BSR r,r/m 2 0 16 0 4 1 alu1 386 SETcc r 2 0 9 0 1 1 int 386 SETcc m 3 0 9 0 2 1 int 386 CLC, STC 2 0 0 8 86 d CMC 3 0 15 0 86 CLD, STD 1 8 0 53 86 Control transfer instructions JMP short/near 1 0 0 0 1 0 alu0 branch 86 JMP far 2 25 154 0 86 m JMP r 3 0 15 0 alu0 branch 86 JMP m(near) 3 0 10 0 alu0 branch 86 JMP m(far) 2 28 157 0 86 Jcc short/near 1 0 2-4 0 alu0 branch 86 J(E)CXZ short 4 0 4 0 alu0 branch 86 LOOP short 4 0 4 0 alu0 branch 86 CALL near 3 0 7 0 alu0 branch 86 CALL far 3 29 160 0 86 m CALL r 4 0 7 0 alu0 branch 86 CALL m(near) 4 0 9 0 alu0 branch 86 CALL m(far) 2 32 160 0 86 RETN 4 0 7 0 alu0 branch 86 RETN i 4 0 7 0 alu0 branch 86 RETF 1 30 160 0 86 RETF i 2 30 160 0 86 IRET 1 49 325 0 86 BOUND m 2 11 12 186 m INT i 2 67 470 86 INTO 1 4 26 86 m Other NOP (90) 1 0 0 0.25 0/1 alu0/1 86 Long NOP (0F 1F) 1 0 0 0.25 0/1 alu0/1 ppro PAUSE 1 2 50 sse2 LEAVE 4 0 5 5 186 CLI 1 5 52 86 STI 1 11 64 86 CPUID 1 49-90 300-500 p5 RDTSC 1 12 100 p5 Page 148
Prescott RDPMC (bit 31 = 1) 1 37 100 p5 RDPMC (bit 31 = 0) 4 154 240 p5 MONITOR (sse3) MWAIT Notes: (sse3) a) Add 1 μop if source is a memory operand. b) Uses an extra μop (port 3) if SIB byte used. c) Add 1 μop if source or destination, but not both, is a high 8-bit register (AH, BH, CH, DH). d) Has (false) dependence on the flags in most cases. e) Not available on PMMX l) Move accumulator to/from memory with 64 bit absolute address (opcode A0 - A3). m) Not available in 64 bit mode. n) Not available in 64 bit mode on some processors. o) MOVSX uses an extra μop if the destination register is smaller than the biggest register size available. Use a 32 bit destination register in 16 bit and 32 bit mode, and a 64 bit destination register in 64 bit mode for optimal performance. p) LEA with a direct memory operand has 1 μop and a reciprocal throughput of 0.25. This also applies if there is a RIP-relative address in 64-bit mode. A signextended 32-bit direct memory operand in 64-bit mode without RIP-relative address takes 2 μops because of the SIB byte. The throughput is 1 in this case. You may use a MOV instead. q) Floating point x87 instructions <strong>Instruction</strong> Operands These values are measured in 32-bit mode. In 16-bit real mode there is 1 microcode μop and a reciprocal throughput of 17. μops Microcode Latency Page 149 Additional latency Reciprocal throughput Move instructions FLD r 1 0 7 0 1 0 mov 87 FLD m32/64 1 0 0 1 2 load 87 FLD m80 3 3 8 2 load 87 FBLD m80 3 74 90 2 load 87 FST(P) r 1 0 7 0 1 0 mov 87 FST(P) m32/64 2 0 7 2 0 store 87 FSTP m80 3 6 10 0 store 87 FBSTP m80 3 311 400 0 store 87 FXCH r 1 0 0 0 1 0 mov 87 FILD m16 3 2 8 2 load 87 FILD m32/64 2 0 2 2 load 87 FIST(P) m 3 0 2.5 0 store 87 FISTTP m 3 0 2.5 0 store sse3 FLDZ 1 0 2 0 mov 87 Port Execution unit Subunit <strong>Instruction</strong> set Notes
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
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Logic AND/ANDN/OR/XORPS/ PD VAND/AN
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Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
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Merom ROR ROL m,i/cl 3 2 x x 1 1 1
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Merom FLDPI FLDL2E etc. 2 2 2 float
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Merom PALIGNR h) xmm,m128,i 2 2 x x
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Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
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Wolfdale Intel Core 2 (Wolfdale, 45
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Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 143 and 144: Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166: VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172: VIA Nano 2000 Floating point XMM in
Page 173 and 174: VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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