4 Instruction tables - Agner Fog

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Pentium 4 Conversion CVTPS2PD r,r/m 4 0 7 1 4 1 mmx shift sse2 a CVTPD2PS r,r/m 2 0 10 1 2 1 fp-mmx sse2 a CVTSD2SS r,r/m 4 0 14 1 6 1 mmx shift sse2 a CVTSS2SD r,r/m 4 0 10 1 6 1 mmx shift sse2 a CVTDQ2PS r,r/m 1 0 4 1 2 1 fp sse2 a CVTDQ2PD r,r/m 3 0 9 1 4 1 mmx-fp sse2 a CVT(T)PS2DQ r,r/m 1 0 4 1 2 1 fp sse2 a CVT(T)PD2DQ r,r/m 2 0 9 1 2 1 fp-mmx sse2 a CVTPI2PS xmm,mm 4 0 10 1 4 1 mmx sse a CVTPI2PD xmm,mm 4 0 11 1 5 1 fp-mmx sse2 a CVT(T)PS2PI mm,xmm 3 0 7 0 2 0,1 fp-mmx sse a CVT(T)PD2PI mm,xmm 3 0 11 1 3 0,1 fp-mmx sse2 a CVTSI2SS xmm,r32 3 0 10 1 3 1 fp-mmx sse a CVTSI2SD xmm,r32 4 0 15 1 6 1 fp-mmx sse2 a CVT(T)SD2SI r32,xmm 2 0 8 1 2.5 1 fp sse2 a CVT(T)SS2SI r32,xmm 2 0 8 1 2.5 1 fp sse a Arithmetic ADDPS/D ADDSS/D r,r/m 1 0 4 1 2 1 fp add sse a SUBPS/D SUBSS/D r,r/m 1 0 4 1 2 1 fp add sse a MULPS/D MULSS/D r,r/m 1 0 6 1 2 1 fp mul sse a DIVSS r,r/m 1 0 23 0 23 1 fp div sse a,h DIVPS r,r/m 1 0 39 0 39 1 fp div sse a,h DIVSD r,r/m 1 0 38 0 38 1 fp div sse2 a,h DIVPD r,r/m 1 0 69 0 69 1 fp div sse2 a,h RCPPS RCPSS MAXPS/D MAXSS/DMINPS/D r,r/m 2 0 4 1 4 1 mmx sse a MINSS/D CMPccPS/D r,r/m 1 0 4 1 2 1 fp add sse a CMPccSS/D r,r/m 1 0 4 1 2 1 fp add sse a COMISS/D UCOMISS/D r,r/m 2 0 6 1 3 1 fp add sse a Logic ANDPS/D ANDNPS/D ORPS/D XORPS/D r,r/m 1 0 2 1 2 1 mmx alu sse a Math SQRTSS r,r/m 1 0 23 0 23 1 fp div sse a,h SQRTPS r,r/m 1 0 39 0 39 1 fp div sse a,h SQRTSD r,r/m 1 0 38 0 38 1 fp div sse2 a,h SQRTPD r,r/m 1 0 69 0 69 1 fp div sse2 a,h RSQRTSS r,r/m 2 0 4 1 3 1 mmx sse a RSQRTPS r,r/m 2 0 4 1 4 1 mmx sse a Other LDMXCSR m 4 8 98 100 1 sse STMXCSR m 4 4 6 1 sse Notes: a) Add 1 μop if source is a memory operand. Page 142
Pentium 4 h) Throughput of FP-MUL unit is reduced during the use of the FP-DIV unit. k) It may be advantageous to replace this instruction by two 64-bit moves. Page 143
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
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Logic AND/ANDN/OR/XORPS/ PD VAND/AN
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Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
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Merom ROR ROL m,i/cl 3 2 x x 1 1 1
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Merom FLDPI FLDL2E etc. 2 2 2 float
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Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91 and 92: Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 93 and 94: Wolfdale Intel Core 2 (Wolfdale, 45
Page 95 and 96: Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150: Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166: VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172: VIA Nano 2000 Floating point XMM in
Page 173 and 174: VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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