4 Instruction tables - Agner Fog

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Pentium 4 MOVD xmm,m32 1 0 ≈ 8 0 1 2 load sse2 MOVD m32, r 2 0 ≈ 8 2 0,1 mmx MOVQ mm,mm 1 0 6 0 1 0 mov mmx MOVQ xmm,xmm 1 0 2 1 2 1 mmx shift sse2 MOVQ r,m64 1 0 ≈ 8 1 2 load mmx MOVQ m64,r 2 0 ≈ 8 2 0 mov mmx MOVDQA xmm,xmm 1 0 6 0 1 0 mov sse2 MOVDQA xmm,m 1 0 ≈ 8 1 2 load sse2 MOVDQA m,xmm 2 0 ≈ 8 2 0 mov sse2 MOVDQU xmm,m 4 0 2 2 load sse2 k MOVDQU m,xmm 4 6 2 0 mov sse2 k MOVDQ2Q mm,xmm 3 0 8 1 2 0,1 mov-mmx sse2 MOVQ2DQ xmm,mm 2 0 8 1 2 0,1 mov-mmx sse2 MOVNTQ m,mm 3 0 75 0 mov sse MOVNTDQ PACKSSWB/DW m,xmm 2 0 18 0 mov sse2 PACKUSWB PACKSSWB/DW mm,r/m 1 0 2 1 1 1 mmx shift mmx a PACKUSWB PUNPCKH/LBW/WD/ xmm,r/m 1 0 4 1 2 1 mmx shift mmx a DQ PUNPCKHBW/WD/DQ/ mm,r/m 1 0 2 1 1 1 mmx shift mmx a QDQ PUNPCKLBW/WD/DQ/Q xmm,r/m 1 0 4 1 2 1 mmx shift sse2 a DQ xmm,r/m 1 0 2 1 2 1 mmx shift sse2 a PSHUFD xmm,xmm,i 1 0 4 1 2 1 mmx shift sse2 PSHUFL/HW xmm,xmm,i 1 0 2 1 2 1 mmx shift sse2 PSHUFW mm,mm,i 1 0 2 1 1 1 mmx shift mmx MASKMOVQ mm,mm 4 4 7 0 mov sse MASKMOVDQU xmm,xmm 4 6 10 0 mov sse2 PMOVMSKB r32,r 2 0 7 1 3 0,1 mmx-alu0 sse PEXTRW r32,mm,i 3 0 8 1 2 1 mmx-int sse PEXTRW r32,xmm,i 3 0 9 1 2 1 mmx-int sse2 PINSRW mm,r32,i 2 0 3 1 2 1 int-mmx sse PINSRW xmm,r32,i 2 0 4 1 2 1 int-mmx sse2 Arithmetic instructions PADDB/W/D PADD(U)SB/W PSUBB/W/D r,r/m 1 0 2 1 1,2 1 mmx alu mmx a,j PSUB(U)SB/W r,r/m 1 0 2 1 1,2 1 mmx alu mmx a,j PADDQ, PSUBQ mm,r/m 1 0 2 1 1 1 mmx alu sse2 a PADDQ, PSUBQ PCMPEQB/W/D xmm,r/m 1 0 4 1 2 1 fp add sse2 a PCMPGTB/W/D r,r/m 1 0 2 1 1,2 1 mmx alu mmx a,j PMULLW PMULHW r,r/m 1 0 6 1 1,2 1 fp mul mmx a,j PMULHUW r,r/m 1 0 6 1 1,2 1 fp mul sse a,j PMADDWD r,r/m 1 0 6 1 1,2 1 fp mul mmx a,j PMULUDQ r,r/m 1 0 6 1 1,2 1 fp mul sse2 a,j PAVGB/W r,r/m 1 0 2 1 1,2 1 mmx alu sse a,j PMIN/MAXUB r,r/m 1 0 2 1 1,2 1 mmx alu sse a,j Page 140
Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1 1,2 1 mmx alu sse a,j PSADBW r,r/m 1 0 4 1 1,2 1 mmx alu sse a,j Logic PAND, PANDN r,r/m 1 0 2 1 1,2 1 mmx alu mmx a,j POR, PXOR PSLL/RLW/D/Q, r,r/m 1 0 2 1 1,2 1 mmx alu mmx a,j PSRAW/D r,i/r/m 1 0 2 1 1,2 1 mmx shift mmx a,j PSLLDQ, PSRLDQ xmm,i 1 0 4 1 2 1 mmx shift sse2 a Other EMMS 4 11 12 12 0 mmx Notes: a) Add 1 μop if source is a memory operand. j) Reciprocal throughput is 1 for 64 bit operands, and 2 for 128 bit operands. k) It may be advantageous to replace this instruction by two 64-bit moves Floating point XMM instructions <strong>Instruction</strong> Operands μops Microcode Latency Page 141 Additional latency Reciprocal throughput Move instructions MOVAPS/D r,r 1 0 6 0 1 0 mov sse MOVAPS/D r,m 1 0 ≈ 7 0 1 2 sse MOVAPS/D m,r 2 0 ≈ 7 2 0 sse MOVUPS/D r,r 1 0 6 0 1 0 mov sse MOVUPS/D r,m 4 0 2 2 sse k MOVUPS/D m,r 4 6 8 0 sse k MOVSS r,r 1 0 2 0 2 1 mmx shift sse MOVSD r,r 1 0 2 1 2 1 mmx shift sse MOVSS, MOVSD r,m 1 0 ≈ 7 0 1 2 sse MOVSS, MOVSD m,r 2 0 2 0 sse MOVHLPS r,r 1 0 4 0 2 1 mmx shift sse MOVLHPS r,r 1 0 2 0 2 1 mmx shift sse MOVHPS/D, MOVLPS/D r,m 3 0 4 2 sse MOVHPS/D, MOVLPS/D m,r 2 0 2 0 sse MOVNTPS/D m,r 2 0 4 0 sse/2 MOVMSKPS/D r32,r 2 0 6 1 3 1 fp sse SHUFPS/D r,r/m,i 1 0 4 1 2 1 mmx shift sse UNPCKHPS/D r,r/m 1 0 4 1 2 1 mmx shift sse UNPCKLPS/D r,r/m 1 0 2 1 2 1 mmx shift sse Port Execution unit Subunit <strong>Instruction</strong> set Notes
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Introduction 4 Instruction tables L
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Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
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Logic AND/ANDN/OR/XORPS/ PD VAND/AN
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Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
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Merom ROR ROL m,i/cl 3 2 x x 1 1 1
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Merom FLDPI FLDL2E etc. 2 2 2 float
Page 89 and 90: Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91 and 92: Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 93 and 94: Wolfdale Intel Core 2 (Wolfdale, 45
Page 95 and 96: Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135 and 136: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 137 and 138: Pentium 4 RETF i 4 33 11 0 86 IRET
Page 139: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 143 and 144: Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150: Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166: VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172: VIA Nano 2000 Floating point XMM in
Page 173 and 174: VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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