4 Instruction tables - Agner Fog

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Pentium 4 NOT m 4 0 ≥ 4 86 SHL, SHR, SAR r,i 1 0 4 1 1 1 int mmxsh 186 SHL, SHR, SAR r,CL 2 0 6 0 1 1 int mmxsh 86 d ROL, ROR r,i 1 0 4 1 1 1 int mmxsh 186 d ROL, ROR r,CL 2 0 6 0 1 1 int mmxsh 86 d RCL, RCR r,1 1 0 4 1 1 1 int mmxsh 86 d RCL, RCR r,i 4 15 16 0 15 1 int mmxsh 186 d RCL, RCR SHL,SHR,SAR,ROL, r,CL 4 15 16 0 14 1 int mmxsh 86 d ROR m,i/CL 4 7-8 10 0 10 1 int mmxsh 86 d RCL, RCR m,1 4 7 10 0 10 1 int mmxsh 86 d RCL, RCR m,i/CL 4 18 18-28 14 1 int mmxsh 86 d SHLD, SHRD r,r,i/CL 4 14 14 0 14 1 int mmxsh 386 SHLD, SHRD m,r,i/CL 4 18 14 0 14 1 int mmxsh 386 BT r,i 3 0 4 0 2 1 int mmxsh 386 d BT r,r 2 0 4 0 1 1 int mmxsh 386 d BT m,i 4 0 4 0 2 1 int mmxsh 386 d BT m,r 4 12 12 0 12 1 int mmxsh 386 d BTR, BTS, BTC r,i 3 0 6 0 2 1 int mmxsh 386 BTR, BTS, BTC r,r 2 0 6 0 4 1 int mmxsh 386 BTR, BTS, BTC m,i 4 7 18 0 8 1 int mmxsh 386 BTR, BTS, BTC m,r 4 15 14 0 14 1 int mmxsh 386 BSF, BSR r,r 2 0 4 0 2 1 int mmxsh 386 BSF, BSR r,m 3 0 4 0 3 1 int mmxsh 386 SETcc r 3 0 5 0 1 1 int 386 SETcc m 4 0 5 0 3 1 int 386 CLC, STC 3 0 10 0 2 86 d CMC 3 0 10 0 2 86 CLD 4 7 52 0 52 86 STD 4 5 48 0 48 86 CLI 4 5 35 35 86 STI 4 12 43 43 86 Control transfer instructions JMP short/near 1 0 0 0 1 0 alu0 branch 86 JMP far 4 28 118 118 0 86 JMP r 3 0 4 4 0 alu0 branch 86 JMP m(near) 3 0 4 4 0 alu0 branch 86 JMP m(far) 4 31 11 11 0 86 Jcc short/near 1 0 0 2-4 0 alu0 branch 86 J(E)CXZ short 4 4 0 2-4 0 alu0 branch 86 LOOP short 4 4 0 2-4 0 alu0 branch 86 CALL near 3 0 2 2 0 alu0 branch 86 CALL far 4 34 0 86 CALL r 4 4 8 0 alu0 branch 86 CALL m(near) 4 4 9 0 alu0 branch 86 CALL m(far) 4 38 0 86 RETN 4 0 2 0 alu0 branch 86 RETN i 4 0 2 0 alu0 branch 86 RETF 4 33 11 0 86 Page 136
Pentium 4 RETF i 4 33 11 0 86 IRET 4 48 24 0 86 ENTER i,0 4 12 26 26 186 ENTER i,n 4 45+24n 128+16n 186 LEAVE 4 0 3 3 186 BOUND m 4 14 14 14 186 INTO 4 5 18 18 86 INT i 4 84 644 86 String instructions LODS 4 3 6 6 86 REP LODS 4 5n ≈ 4n+36 86 STOS 4 2 6 6 86 REP STOS 4 2n+3 ≈ 3n+10 86 MOVS 4 4 6 4 86 REP MOVS 4 ≈163+1.1n 86 SCAS 4 3 6 86 REP SCAS 4 ≈ 40+6n ≈4n 86 CMPS 4 5 8 86 REP CMPS 4 ≈ 50+8n ≈4n 86 Other NOP (90) 1 0 0 0.25 0/1 alu0/1 86 Long NOP (0F 1F) 1 0 0 0.25 0/1 alu0/1 ppro PAUSE 4 2 sse2 CPUID 4 39-81 200-500 p5 RDTSC Notes: 4 7 80 p5 a) Add 1 μop if source is a memory operand. b) Uses an extra μop (port 3) if SIB byte used. A SIB byte is needed if the memory operand has more than one pointer register, or a scaled index, or ESP is used as base pointer. c) Add 1 μop if source or destination, but not both, is a high 8-bit register (AH, BH, CH, DH). d) Has (false) dependence on the flags in most cases. e) Not available on PMMX q) Latency is 12 in 16-bit real or virtual mode, 24 in 32-bit protected mode. Floating point x87 instructions <strong>Instruction</strong> Operands μops Microcode Latency Page 137 Additional latency Reciprocal throughput Move instructions FLD r 1 0 6 0 1 0 mov 87 FLD m32/64 1 0 ≈ 7 0 1 2 load 87 Port Execution unit Subunit <strong>Instruction</strong> set Notes
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Introduction 4 Instruction tables L
Page 3 and 4:
Definition of terms Operands Latenc
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Definition of terms It is not possi
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AMD K7 AMD K7 List of instruction t
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AMD K7 IMUL r32,r32/m32 2 4 2.5 ALU
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AMD K7 Other NOP (90) 1 0 1/3 ALU L
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AMD K7 PUNPCKH/LBW/WD mm,r/m 1 2 2
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AMD K7 Integer instructions PAVGUSB
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MOVNTI m,r 1 2-3 AGU MOVZX, MOVSX r
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RCL, RCR m,1 1 7 4 ALU, AGU RCL m,i
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K8 FNSTSW m16 2 8 FMISC, ALU do. FN
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PADDB/W/D/Q PADDSB/W PADDUSB/W PSUB
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MAXSS/D MINSS/D r,r/m 1 2 1 FADD MA
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K10 MOVNTI m,r 1 1 AGU MOVZX, MOVSX
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K10 RCR m,CL 8 7 5 ALU, AGU SHLD, S
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K10 FADD(P),FSUB(R)(P) r/m 1 4 1 FA
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K10 PADDB/W/D/Q PADDSB/W PADDUSB/W
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K10 LDMXCSR m 12 12 10 STMXCSR m 3
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Bulldozer Integer instructions Inst
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Bulldozer TEST m,r 1 0.5 EX01 TEST
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Bulldozer FLD m80 8 14 4 fp FBLD m8
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Bulldozer MASKMOVQ mm,mm 31 38 37 P
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Bulldozer MOVDDUP x,x 1 2 1 P1 ivec
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Logic AND/ANDN/OR/XORPS/ PD VAND/AN
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Bobcat AMD Bobcat List of instructi
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Bobcat IMUL r16,(r16),i 2 4 3 I0 IM
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Bobcat Move instructions FLD r 1 2
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Bobcat PUNPCKH/LBW/WD/ DQ PUNPCKH/L
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Bobcat MOVSHDUP, MOVSLDUP r,m 2 12
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Intel Pentium Intel Pentium and Pen
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Intel Pentium REP MOVS 12+n g) np S
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s Intel Pentium May be up to 3 cloc
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Pentium II and III PUSHF(D) 3 11 1
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Pentium II and III a) Faster under
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Pentium II and III PMOVMSKB d) r32,
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Pentium M Intel Pentium M, Core Sol
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Pentium M DIV IDIV r16 4 3 1 15-24
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Pentium M FLD r 1 1 1 FLD m32/64 1
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Pentium M MOVNTDQ PACKSSWB/DW m128,
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Pentium M MOVUPS/D m128,xmm 8 4 2 2
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Pentium M RSQRTSS xmm,xmm 1 1 3 1 R
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Merom Move instructions MOV r,r/i 1
Page 85 and 86: Merom ROR ROL m,i/cl 3 2 x x 1 1 1
Page 87 and 88: Merom FLDPI FLDL2E etc. 2 2 2 float
Page 89 and 90: Merom PALIGNR h) xmm,m128,i 2 2 x x
Page 91 and 92: Merom UNPCKH/LPD xmm,m128 2 1 1 1 f
Page 93 and 94: Wolfdale Intel Core 2 (Wolfdale, 45
Page 95 and 96: Wolfdale ADC SBB r,m 2 2 x x x 1 2
Page 97 and 98: Wolfdale LODS 3 2 1 1 REP LODS 4+7n
Page 99 and 100: Wolfdale Other FNOP 1 1 1 float 1 W
Page 101 and 102: Wolfdale Arithmetic instructions PA
Page 103 and 104: Wolfdale SHUFPS xmm,m128,i 2 1 1 1
Page 105 and 106: Wolfdale DPPD j) xmm,m128,i 4 4 x x
Page 107 and 108: Latency: Reciprocal throughput: Neh
Page 109 and 110: Nehalem CBW CWDE CDQE 1 1 x x x int
Page 111 and 112: Nehalem Floating point x87 instruct
Page 113 and 114: Nehalem MOVNTDQA j) PACKSSWB/DW PAC
Page 115 and 116: Nehalem PHMINPOSUW j) PABSB PABSW P
Page 117 and 118: Nehalem CVTDQ2PS xmm,xmm 1 1 1 floa
Page 119 and 120: Sandy Bridge Intel Sandy Bridge Lis
Page 121 and 122: Sandy Bridge INC DEC NEG NOT r 1 1
Page 123 and 124: Sandy Bridge CALL m 3 2 1 2 1 2 RET
Page 125 and 126: Sandy Bridge FYL2XP1 464 464 726 FP
Page 127 and 128: Sandy Bridge PCMPEQ/GTB/W/D (x)mm,m
Page 129 and 130: Sandy Bridge MOVMSKPS/D r32,x 1 1 1
Page 131 and 132: Sandy Bridge ADDSS/D SUBSS/D x,x 1
Page 133 and 134: Pentium 4 Intel Pentium 4 List of i
Page 135: Pentium 4 SFENCE 4 2 40 sse LFENCE
Page 139 and 140: Pentium 4 Math FSQRT 1 0 43 0 43 1
Page 141 and 142: Pentium 4 PMIN/MAXSW r,r/m 1 0 2 1
Page 143 and 144: Pentium 4 h) Throughput of FP-MUL u
Page 145 and 146: Prescott MOV r64,i64 2 0 0 1 1 alu1
Page 147 and 148: Prescott IDIV r8/m8 1 21 76 0 34 1
Page 149 and 150: Prescott RDPMC (bit 31 = 1) 1 37 10
Page 151 and 152: Prescott Other FNOP 1 0 1 0 1 0 mov
Page 153 and 154: Prescott Other EMMS Notes: 10 10 12
Page 155 and 156: Atom Intel Atom List of instruction
Page 157 and 158: Atom IMUL r16,r16 2 ALU0, Mul 6 5 I
Page 159 and 160: Atom NOP (90) 1 ALU0/1 1/2 Long NOP
Page 161 and 162: Atom PACKSSWB/DW PACKUSWB (x)mm, (x
Page 163 and 164: Atom HADDPS HSUBPS xmm,xmm 5 FP0+1
Page 165 and 166: VIA Nano 2000 MOVSX MOVSXD MOVZX r,
Page 167 and 168: VIA Nano 2000 SETcc m 1 CLC STC CMC
Page 169 and 170: VIA Nano 2000 FABS 1 MB 1 1 FCHS 1
Page 171 and 172: VIA Nano 2000 Floating point XMM in
Page 173 and 174: VIA Nano 2000 REP XCRYPTECB 192 bit
Page 175 and 176: Nano 3000 MOVSX MOVZX r,r 1 I12 1 1
Page 177 and 178: Nano 3000 Control transfer instruct
Page 179 and 180: Nano 3000 FCOMPP FUCOMPP 1 MB 1 FCO
Page 181 and 182: PABSB PABSW PABSD PSIGNB PSIGNW PSI
Page 183: Nano 3000 Other LDMXCSR m32 31 STMX
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4 Instruction tables - Agner Fog

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