4 Instruction tables - Agner Fog

Nehalem
Fused compare/test and branch e) 1 1 1 int 0 2
J(E/R)CXZ short 2 2 x x 1 int 2
LOOP short 6 6 x x x int 4
LOOP(N)E short 11 11 x x x int 7
CALL near 2 2 1 1 1 int 2
CALL i) far 46 46 9 int 74
CALL r 3 2 1 1 1 int 2
CALL m(near) 4 3 1 1 1 1 int 2
CALL m(far) 47 47 1 int 79
RETN 1 1 1 1 int 2
RETN i 3 2 1 1 int 2
RETF 39 39 int 120
RETF i 40 40 int 124
BOUND i) r,m 15 13 2 int 7
INTO i) 4 4 int 5
String instructions
LODS 2 1 x x x 1 int 1
REP LODS 11+4n int 40+12n
STOS 3 1 x x x 1 1 int 1
REP STOS small n 60+n int 12+n
REP STOS large n 2.5/16 bytes int 1 clk / 16 bytes
MOVS 5 2 x x x 1 1 1 int 4
REP MOVS small n 13+6n int 12+n
REP MOVS large n 2/16 bytes int 1 clk / 16 bytes
SCAS 3 2 x x x 1 int 1
REP SCAS 37+6n int 40+2n
CMPS 5 3 x x x 2 int 4
REP CMPS 65+8n int 42+2n
Other
NOP (90) 1 1 x x x int 0.33
Long NOP (0F 1F) 1 1 x x x int 1
PAUSE 5 5 x x x int 9
ENTER a,0 11 9 x x x 1 1 1 int 8
ENTER a,b 34+7b int 79+5b
LEAVE 3 3 1 int 5
CPUID 25-100 int ~200 ~200
RDTSC 22 int 24
RDPMC
Notes:
28 int 40-60
a) Applies to all addressing modes
b) Has an implicit LOCK prefix.
c) Low values are for small results, high values for high results.
e)
See manual 3: "The microarchitecture of Intel, AMD and VIA CPUs" for restrictions
on macro-op fusion.
i) Not available in 64 bit mode.
ℓ) SSE4.2 instruction set.
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