4 Instruction tables - Agner Fog

Latency:
Reciprocal throughput:
Nehalem
This is the delay that the instruction generates in a dependency chain. The
numbers are minimum values. Cache misses, misalignment, and exceptions
may increase the clock counts considerably. Floating point operands are presumed
to be normal numbers. Denormal numbers, NAN's and infinity increase
the delays very much, except in XMM move, shuffle and Boolean instructions.
Floating point overflow, underflow, denormal or NAN results give a similar
delay. The time unit used is core clock cycles, not the reference clock cycles
given by the time stamp counter.
The average number of core clock cycles per instruction for a series of independent
instructions of the same kind in the same thread.
Integer instructions
Instruction Operands μops μops unfused domain DoLatenReci- fused
maincyprocaldomain p015 p0 p1 p5 p2 p3 p4
throughput
Move instructions
MOV r,r/i 1 1 x x x int 1 0.33
MOV a) r,m 1 1 int 2 1
MOV a) m,r 1 1 1 int 3 1
MOV m,i 1 1 1 int 3 1
MOV r,sr 1 1 int 1
MOV m,sr 2 1 1 1 int 1
MOV sr,r 6 3 x x x 3 int 13
MOV sr,m 6 2 x x 4 int 14
MOVNTI
MOVSX MOVZX
m,r 2 1 1 int ~270 1
MOVSXD
MOVSX MOVZX
r,r 1 1 x x x int 1 0.33
MOVSXD
r,m 1 1 int 1
CMOVcc r,r 2 2 x x x int 2 1
CMOVcc r,m 2 2 x x x 1 int
XCHG r,r 3 3 x x x int 2 2
XCHG r,m 7 1 1 1 int 20 b)
XLAT 2 1 1 int 5 1
PUSH r 1 1 1 int 3 1
PUSH i 1 1 1 int 1
PUSH m 2 1 1 1 int 1
PUSH sr 2 1 1 1 int 1
PUSHF(D/Q) 3 2 x x x 1 1 int 1
PUSHA(D) i) 18 2 x 1 x 8 8 int 8
POP r 1 1 int 2 1
POP (E/R)SP 3 2 x 1 x 1 int 5
POP m 2 1 1 1 int 1
POP sr 7 2 5 int 15
POPF(D/Q) 8 7 x x x 1 int 14
POPA(D) i) 10 2 8 int 8
LAHF SAHF 1 1 x x x int 1 0.33
SALC i) 2 2 x x x int 4 1
LEA a) r,m 1 1 1 int 1 1
BSWAP r32 1 1 1 int 1 1
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