4 Instruction tables - Agner Fog

Nehalem
Intel Nehalem
List of instruction timings and μop breakdown
Explanation of column headings:
Operands:
i = immediate data, r = register, mm = 64 bit mmx register, xmm = 128 bit xmm
register, (x)mm = mmx or xmm register, sr = segment register, m = memory,
m32 = 32-bit memory operand, etc.
μops fused domain:
μops unfused domain:
The number of μops at the decode, rename, allocate and retirement stages in
the pipeline. Fused μops count as one.
The number of μops for each execution port. Fused μops count as two. Fused
macro-ops count as one. The instruction has μop fusion if the sum of the numbers
listed under p015 + p2 + p3 + p4 exceeds the number listed under μops
fused domain. An x under p0, p1 or p5 means that at least one of the μops listed
under p015 can optionally go to this port. For example, a 1 under p015 and
an x under p0 and p5 means one μop which can go to either port 0 or port 5,
whichever is vacant first. A value listed under p015 but nothing under p0, p1
and p5 means that it is not known which of the three ports these μops go to.
p015: The total number of μops going to port 0, 1 and 5.
p0: The number of μops going to port 0 (execution units).
p1: The number of μops going to port 1 (execution units).
p5: The number of μops going to port 5 (execution units).
p2: The number of μops going to port 2 (memory read).
p3: The number of μops going to port 3 (memory write address).
p4: The number of μops going to port 4 (memory write data).
Domain:
Tells which execution unit domain is used: "int" = integer unit (general purpose
registers), "ivec" = integer vector unit (SIMD), "fp" = floating point unit (XMM
and x87 floating point). An additional "bypass delay" is generated if a register
written by a μop in one domain is read by a μop in another domain. The bypass
delay is 1 clock cycle between the "int" and "ivec" units, and 2 clock cycles
between the "int" and "fp", and between the "ivec" and "fp" units.
The bypass delay is indicated under latency only where it is unavoidable because
either the source operand or the destination operand is in an unnatural
domain such as a general purpose register (e.g. eax) in the "ivec" domain. For
example, the PEXTRW instruction executes in the "int" domain. The source
operand is an xmm register and the destination operand is a general purpose
register. The latency for this instruction is indicated as 2+1, where 2 is the
latency of the instruction itself and 1 is the bypass delay, assuming that the
xmm operand is most likely to come from the "ivec" domain. If the xmm operand
comes from the "fp" domain then the bypass delay will be 2 rather than
one. The flags register can also have a bypass delay. For example, the
COMISS instruction (floating point compare) executes in the "fp" domain and
returns the result in the integer flags. Almost all instructions that read these
flags execute in the "int" domain. Here the latency is indicated as 1+2, where 1
is the latency of the instruction itself and 2 is the bypass delay from the "fp"
domain to the "int" domain.
The bypass delay from the memory read unit to any other unit and from any
unit to the memory write unit are included in the latency figures in the table.
Where the domain is not listed, the bypass delays are either unlikely to occur or
unavoidable and therefore included in the latency figure.
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