Variation-Aware Custom IC Design - Solido Design Automation

Variation-Aware Custom IC Design 

Abstract 

Variation-Aware Custom IC Design: 

Improving PVT and Statistical Maximum Yield at the Performance Edge 

Variation has become a critical concern in 

modern process geometries; managing it 

properly is key in designing custom circuits with 

competitive performance, power, and area. This 

paper describes how a flow using design-specific 

corners manages variation issues in a unified 

fashion. To enable corner-based design, the key 

ingredients are corner extraction and design 

verification tools. This paper describes such 

tools for PVT, 3-sigma Monte Carlo, and highsigma 

design; and how appropriate technology 

can make these tools fast, accurate, and 

scalable. Finally, as an example, this paper 

focuses on high-sigma problems, showcasing 

High-Sigma Monte Carlo (HSMC) which 

analyzes billions of Monte Carlo samples in 

minutes, with SPICE accuracy. 

Introduction 

In today’s highly competitive semiconductor 

industry, profitability hinges on competitive 

design performance, high yield, and rapid time to 

market. This is even becoming even more 

pronounced as leading-edge designs push into 

smaller process nodes. Due to the common use 

of foundries like TSMC and Global Foundries, 

silicon technology is no longer a differentiating 

factor. Advantages in performance, power, and 

area will be key to market success. Custom 

integrated circuit design is key to gain such 

differentiation. Beyond analog, custom IC 

design includes RF, high-speed I/O, standard cell 

digital library and memory design. 

and Global process variation, local process 

variation, environmental variation affect custom 

circuit performance; and designers must manage 

this under tight performance, power, yield, and 

time constraints. Depending on the type of 

variation-design problem, designers face 

numerous challenges. We now explore these 

challenges, for each problem type. 

PVT. In some cases, a PVT-corners approach to 

variation may be enough, in which global F/S 

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corners model process variation. Even that, 

however, can be cumbersome: running a 

comprehensive range of PVT corners can take 

days. Designers may try to overcome this by 

guessing which corner combinations are most 

appropriate, which increases design risk. They 

may try to reduce risk by adding margins, at the 

expense of performance, power, or area. 

Monte Carlo (3-Sigma) Statistical. In many 

design problems, global F/S corners are not 

accurate enough; statistical models of the global 

and local process distribution are necessary. 

Designers could use Monte Carlo sampling, but 

design iterations against Monte Carlo sampling 

are time-consuming (days not hours). 

Alternatively, designers could use PVT corners, 

which increases design risk. 

High-Sigma Statistical. Circuits like bitcells, 

sense amps, and standard cell digital library 

circuits are replicated thousands or millions of 

times, and therefore must have very low failure 

rate (e.g. 1 in a million). Designers could use a 

big Monte Carlo run, but that is extremely timeconsuming 

(e.g. 1 million samples just to get 1 

failure). Alternatively, designers could use a 

small Monte Carlo run and extrapolate with 

density estimation, but that will be inaccurate 

because there will be no information at the tails. 

Or, designers could develop an analytical model, 

but it is time-consuming to create and verify, and 

is topology-specific. 

There is a pattern here; regardless of variation 

problem type, designers face similar dilemmas. 

They could use an accurate model but have slow 

design iterations. Alternatively, they could 

loosen the model for fast design iterations, but 

that risks design failures (under-design), or 

compromises performance / power / area (overdesign). 

Figure 1 illustrates. 

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Figure 1: If variation is poorly handled, the 

design may compromise performance / power 

/ area due to excessive safety (over-design); or 

yield due to due to variations (under-design). 

This paper asks: can this dilemma be resolved, 

so that designers can have rapid design 

iterations, yet use an accurate model of variation 

so that over- and under-design is avoided? The 

answer lies in using appropriately chosen designspecific 

corners – a small representative set that 

simulates quickly, yet captures the bounds of the 

performance distribution. 

Design-Specific Corners 

Figure 2 shows a methodology for variationaware 

design using design-specific corners. The 

general idea is to do rapid design iterations 

against a small set of design-specific corners, yet 

use verification to confirm with confidence that 

the design is good. 

Figure 2: Corner-based design flow. This 

flow applies to PVT, Monte Carlo, or High- 

Sigma variation problems. 

In the first step of the flow, the circuit is verified 

using a verification tool. If the design is 

acceptable, the flow is complete. If not, 

representative corners are extracted, and the loop 

is repeated. 

For each type of problem variation, there is a 

specific tool for verification and for corner 

extraction - PVT, Monte Carlo Statistical, and 

High-Sigma Statistical. 

The user can combine the flows for different 

variation problems. For example, the user could 

do a first-cut design using just a single nominal 

corner, then add some PVT corners and design 

against them, and finally add Monte Carlo 

Statistical corners. 

Enabling Technologies for Design- 

Specific Corners 

Naïve implementations of verification and corner 

extraction tools are not adequate; these tools 

must be fast, accurate, and scalable. Fortunately, 

appropriate technologies now exist to achieve 

these goals. 

The key to fast, accurate, and scalable PVT 







verification and corner extraction is to cast it as a 

global optimization problem, then to solve the 

problem with a fast, reliable optimizer. Such an 

optimizer makes maximal use of the simulations 

taken so far, to make the best-informed decisions 

about what PVT corner regions should be tested. 

Such an approach enables speedups averaging 

10x over naïve approaches. 

Monte Carlo Statistical verification can exploit 

Optimal Spread Sampling for 1.5x to 10x 

speedup over naïve Monte Carlo, at no loss in 

accuracy. Monte Carlo Statistical Corner 

extraction extracts corners at pre-specified target 

yields, leveraging density estimation, response 

surface modeling, and nonlinear programming 

for corners that are 5x-10x more accurate than 

naïve Monte Carlo corners. 

For High-Sigma Statistical problems, High- 

Sigma Monte Carlo (HSMC) can analyze 

billions of Monte Carlo samples in minutes, to 

identify statistical tails with full SPICE accuracy. 

The next section will elaborate. 

Case Study: High Sigma Circuits 

This section is a case study to illustrate variation 

problems on one of the variation problem types: 

high-sigma circuits. High-σ circuits include 

memory elements and highly replicated digital 

blocks. High-σ circuit problems not only need 

accurate statistical modeling, but also deal with 

statistically rare events because the circuit blocks 

are repeated thousands, millions, or even billions 

of times on a die. They have a very rare 

probability of failure (e.g. 1 in a million), for 

which one would need extremely large Monte 

Carlo runs (e.g. 1 million samples just to get 1 

failure). 

Status Quo Approaches in High-σ 

Verification 

For the overall chip to have good yield, the 

repeated high-σ block must have extremely high 

yield (low probability-of-failure pf). Let us 

consider a chip with target yield of 99.0% (pf 

≤0.01), having 1 million bitcells, such as Figure 

3. To achieve the target chip yield, each bitcell 

needs yield ≥ 99.999999% (pf ≤1.0e-8) 1 . 

Let us consider how one might compute the yield 

of such a circuit. 

Plain Monte Carlo (MC): One approach would 

be to use Monte Carlo sampling. However, this 

would require far too many simulations: a circuit 

with 99.9999% yield would need, on average, 1 

million samples from the true distribution just to 

observe a single failure against circuit 

specifications. This is clearly not feasible. 

Figure 3: Failures with rare probability of 

occurrence 

MC with Extrapolation: This approach runs a 

large, but feasible number of MC simulations 

(e.g. 100K or 1M), then extrapolates the results 

to the region of interest. Extrapolation is 

typically done using curve fitting or density 

estimation. The benefits of this approach are that 

it is simple to understand and implement, and the 

results are at least trustworthy within the 

1 For simplicity of description, this assumes that we 

have just local (not global) process variations, and 

there is no redundancy, error correction, etc. Note that 

the algorithm described herein accounts for both local 

and global variations. 







sampling region. Unfortunately, it is timeconsuming 

to run 100K or 1M samples, and 

extrapolation assumes that the behavior in the 

extreme tails of the distribution is consistent with 

that observed at lower sigma. This assumption 

can be misleading, as there may be drop-offs or 

discontinuities in the extreme tails; for example, 

if a device goes out of saturation when a given 

level of variation is applied. 

Manual Model: A third approach is to 

manually construct analytical models relating 

process variation to performance and yield. 

However, this is highly time-consuming to 

construct, is only valid for the specific circuit 

and process, and may have accuracy issues. A 

change to the circuit or process renders the 

model obsolete. 

Importance Sampling (IS): In this approach 

[2][3], the general idea is to change the sampling 

distribution so that more samples are in the 

region of failure. 

An archetypical IS approach for circuit analysis 

is [4], which finds a “center” by solving an 

optimization formulation: “find the process point 

that minimizes the distance to nominal, subject 

to being infeasible.” It then changes the 

sampling distribution to have means at this 

“center”. IS continually draws and simulates 

samples from the new distribution. IS calculates 

yield by assigning a weight to each sample based 

on the point’s probability density on the original 

and new sampling distributions. 

[4] and other IS approaches for circuits were 

demonstrated on problems of ≤12 random 

process variables. But recall that for accurate 

industrial models of process variation, there are 

5, 10, or more process variables per device. This 

means that even for a 6T bitcell, there may be 

≥30 process variables; and sense amp problems 

can have 125 process variables or more. 

While IS has strong int or more intuitive appeal, 

it turns out to have very poor scalability in the 

number of process variables, causing inaccuracy. 

Here’s why: the center-finding step needs to find 

the most probable points that cause infeasibility; 

if it is off even by a bit then the average weight 

of the infeasible samples will be too low, giving 

estimates of yield that are far too optimistic. For 

example, in running [Kanj] on a 185-variable flip 

flop problem, we found that the weights of 

infeasible samples were < 1e-200, compared to 

feasible sample weights of 1e-2 to 1e-0. This 

resulted in an estimated probability of failure of 

≈1e-200, which is obviously wrong compared to 

the “golden” probability of failure of 4.4e-4 

(found by a big MC run). 

To reliably find the most probable points 

amounts to a global optimization problem, which 

has exponential complexity in the number of 

process variables – it can handle 6 or 12 

variables (search space of ≈10 6 or 10 12 ), but not 

e.g. 30 or 125 as in the industrial bitcell and 

sense amp problems given before (space of 10 30 

or 10 125 ). 

None of the previous approaches are adequate. 

Clearly, there is a need to quickly and accurately 

estimate yield for high-yield circuits. 

Furthermore, in the case when yield needs to be 

improved, there is no means to do rapid 

iterations on high-yield circuit designs. 

High-Sigma Monte Carlo (HSMC) 

While IS sounds promising, its reliability is 

hindered by the need to solve a global 

optimization problem of order 10 30 to 10 125 . 

Perhaps we can then reframe the problem and 

associated complexity, by operating on a finite 

set of MC samples. If we have 1B MC samples, 

then that is an upper complexity of 10 9 . While 

“just” 10 9 is much better than the 10 125 

complexity of IS, it is still too expensive to 

simulate 1B MC samples. But what if we were 

sneaky about which MC samples we actually 

simulated? Let us use an approach that 

prioritizes simulations towards the most-likelyto-fail 

cases. It never does an outright rejection 

of samples in case they cause failures; it merely 

de-prioritizes them. It can learn how to prioritize 

using modern machine learning, adapting based 

on feedback from SPICE. By never fully 

rejecting a sample, it is not susceptible to 

inaccurate models; model inaccuracy simply 







adds some noise to convergence, as we shall see 

later. 

This is the core of the High-Sigma Monte Carlo 

(HSMC) approach. 

The HSMC method then produces, typically in 

hundreds or a few thousand simulations: 

� An accurate view of the extreme tail of the 

output distributions (e.g. in NQ form), using 

real MC samples and SPICE-accurate 

results. Since this gives a tradeoff between 

yield and spec, one may get accurate yield 

estimate for a given spec; or spec estimates 

for a given target sigma (yield). 

� A set of MC and SPICE-accurate worst-case 

high-sigma corners, which can be 

subsequently for rapid design iterations. 

HSMC Illustrative Results 

This section demonstrates HSMC’s behavior on 

a suite of designs. The purpose of this section is 

to show how HSMC works in practice on actual 

designs, and purposely includes both cases 

where HSMC works very effectively and cases 

where HSMC is less effective. 

We demonstrate HSMC on a bitcell, having >30 

process variables. 

Experimental Setup. The experimental 

methodology is as follows. We drew N=1M 

Monte Carlo samples and simulated them. These 

form our “golden” results. We set the output 

specification such that 100 of the N samples fail 

spec. Then, we ran HSMC on the problem, with 

Ngen = N, using the same random seed so that it 

has exactly the same generated MC samples. 

HSMC ran for 20K simulations. We repeat the 

procedure with specs set such that 10 of the Ngen 

samples fail spec. 

Results. On this bitcell test case, HSMC finds 

the first 100 failures within its first 5000 samples 

(see Figure 4). Note that with 1.5 million 

samples containing 100 failures, MC will 

typically not find a single failure within 5000 

samples. 

Figure 4: Bitcell cell_i – number of failures 

found vs. sample number (100 failures exist) 

Figure 5 shows results on a normal quantile 

(NQ) plot, which shows distributions but makes 

it easy to examine tails. Each black dot or red 

dot represents an individual simulation. 

The plot compares (i) the results of MC with 1M 

simulations, (ii) HSMC with 100M generated 

samples but just 5500 simulations, (iii) linearextrapolated 

MC, and (iv) quadratic-extrapolated 

MC. All results are presented on a normal 

quantile (NQ) plot to facilitate extrapolation. 

We see that within just a few thousand 

simulations, HSMC can accurately find the tail, 

of what would normally take 100M simulations. 

In contrast, linear and quadratic approximations 

are not able to capture even the tails of 1M MC 

samples, let alone 100M MC samples. 

Figure 5: NQ plot for bitcell cell_i: 1M MC 

samples and 5500/100M HSMC samples, with 

linear and quadratic extrapolation curves 







Conclusion 

Semiconductor profitability hinges on high yield, 

competitive design performance, and rapid time 

to market. For the designer, this translates to the 

need to manage diverse variations (global and 

local process variations, environmental 

variations, etc.), reconcile yield with 

performance (power, speed, area, etc.), while 

under intense time pressures. 

A flow using design-specific corners enables 

designers to manage variation effectively, 

because the corners simulate quickly yet 

represent the performance bounds. 

An example application is high-σ design, where 

failures are one in a million, previous approaches 

to verifying those designs were either extremely 

expensive or inaccurate. High-Sigma Monte 

Carlo (HSMC) allows the designer to quickly 

and accurately verify high-σ designs. 

Furthermore, it enables rapid design iterations, 

via design-specific high-σ corners. 

About Solido 

Solido Variation Designer is a comprehensive set 

of tools for variation-aware custom IC design. It 

allows users to handle PVT, Monte Carlo, and 

High-Sigma problems. 

For each problem type, Solido offers the 

designer easy-to-use tools to analyze variation 

effects, identify transistor sensitivities to 

variation, and fix the design to meet 

specifications with optimal performance, power 

and area. Compared to status quo approaches, 

these tools are more scalable, and up to 10x+ 

faster with SPICE-level accuracy. 

Solido Variation Designer uses foundry models, 

integrates in existing custom IC design flows, 

and supports Cadence Spectre, Synopsys 

HSPICE, Magma / Synopsys FineSim, Mentor 

Eldo and Berkeley Design Automation AFS 

simulators. 

References 

[1] P. G. Drennan, C. C. McAndrew, “Understanding 

MOSFET Mismatch for Analog Design,” IEEE J. 

Solid State Circuits, March 2003. 

[2] T.C. Hesterberg, Advances in importance 

sampling. Ph.D. Dissertation, Statistics Dept., 

Stanford University, 1988 

[3] D.E. Hocevar, M.R. Lightner, and T.N. Trick, “A 

Study of Variance Reduction Techniques for 

Estimating Circuit Yields”, IEEE Trans. 

Computer-Aided Design of Integrated Circuits 

and Systems 2 (3), July 1983, pp. 180-192 

[4] M. Qazi, M. Tikekar, L. Dolecek, D. Shah, and 

A. Chandrakasan, “Loop Flattening & Spherical 

Sampling: Highly Efficient Model Reduction 

Techniques for SRAM Yield Analysis,” 

Proc. Design Automation and Test in Europe, 

March 2010

Variation-Aware Custom IC Design - Solido Design Automation

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