Voltage References

Data Buffer Design
The data buffer is designed as follows:
fo = 200 Hz
Cl = C2 = 0.Q1 J.LF
Q = 0.707 (target)
K = 3.2 (data buffer open loop voltage gain)
Setting Cl = C2 yields:
1
fo = 2nC1VR1R2
Q = JR2 1 JRl
Rl +(2-K) R2
Iteration yields R2 = 4.2 (Rl) to make Q = 0.707.
Substitution into the equation for fo yields:
Rl = 38 kfl (use 39 kfl)
R2 = 4.2 (Rl) = 180 kfl
Cl = C2 = 0.01 J.LF
MC3367
MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-105
Audio Buffer Design
The audio buffer is designed as follows:
fo = 3000 Hz
R 1 = R2 = 8.2 kfl
Q = 0.707 (target)
K = 4.0 (audio buffer open loop voltage gain)
Setting Rl = R2 yields:
1
fo = 27TRl v