Sable CPU Module Specification

CHAPTER 4
FUNCTIONS LOCATED ELSEWHERE ON THE CPU MODULE
4.1 Back-up Cache (B-Cache)
The B-Cache is a 1 Mbyte direct mapped physical write back cache. A 4 Mbyte cache
may be used in future Sable systems. It has a fixed 32-byte block size and supports
the System-bus snooping protocol to allow for a multi-processor implementation.
Each cache block entry is made up of three functionally identifiable storage element
arrays. The control store, which is parity protected, contains the binary flags which
indicate whether a particular cache block entry valid, dirty, and/or shared. The tag
store, which is also parity protected, contains the high order address bits of the data
currently stored in that particular cache block entry. The data store, which is EDC
protected, contains the actual 32 bytes of ‘‘cached’’ data.
Figure 40: Back-up Cache Entry
Control Tag Data
Store Store
Store
P V S D P TAG EDC7 LW7 EDC6 LW6 EDC5 LW5 EDC4 LW4
EDC3 LW3 EDC2 LW2 EDC1 LW1 EDC0 LW0
For a complete description of the B-Cache allocation policy refer to CPU Module
Transactions Chapter 5.
4.1.1 Control Store
The Control Store of the B-Cache is where the binary flags indicating the status of
the cache block are found. These flags are defined in Table 26. To learn how to
initialize any of these bit flags onpower-up refer to Section 9.2.
Functions located elsewhere on the CPU module 83