Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Table 25 (Cont.): Syndromes for Single-Bit Errors Copyright © 1993 Digital Equipment Corporation. Data Bit Syndrome(Hex) Check Bit Syndrome(Hex) 12 2A 13 2C 14 31 15 34 16 0E 17 0B 18 13 19 15 20 16 21 19 22 1A 23 1C 24 62 25 64 26 67 27 68 28 6B 29 6D 30 70 31 75 NOTE A syndrome of 1F is invalid and indicates that a bad EDC code was written intentionally into the cache. This is done when bad data is provided by the System-bus to the C4 interface. A syndrome of 0 indicates that no EDC error was detected. 3.9.11 Backup Cache Tag Register (BC_TAG) BC_TAG is a read-only IPR. Unless locked, the BC_TAG register is loaded with the results of every backup cache tag probe. When a tag or tag control parity error or primary fill data error (parity or EDC) occurs this register is locked against further updates. Software may read the LSB of this register by using the HW_MFPR instruction. Each time an HW_MFPR from BC_TAG completes the contents of BC_ TAG are shifted one bit position to the right, so that the entire register may be read using a sequence of HW_MFPRs. Software may unlock the BC_TAG register using a HW_MTPR to BC_TAG. Successive HW_MFPRs from the BC_TAG register must be separated by at least one null cycle. Functions Located on the DECchip 21064 79
Copyright © 1993 Digital Equipment Corporation. Figure 39: BC_TAG 63 23 22 21 5 4 3 2 1 0 RAZ RO TAG [33..17] RO RO RO RO RO Unused tag bits in the TAG field of this register are always clear, based on the size of the external cache as determined by the BC_SIZE field of the BIU_CTL register. 80 Functions Located on the DECchip 21064 HIT TAGCTL_P TAGCTL_D TAGCTL_S TAGCTL_V TAG_P BC_TAG
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 45 and 46: Copyright © 1993 Digital Equipment
Page 95: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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