Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

3.9.9 Fill Address Register (FILL_ADDR) Copyright © 1993 Digital Equipment Corporation. This read-only register contains the physical address associated with errors reported by BIU_STAT[14..8]. Its contents are meaningful only when FILL_EDC or FILL_ DPERR is set. Reads of FILL_ADDR unlock FILL_ADDR, BIU_STAT[14..8] and FILL_SYNDROME. In the 21064, FILL_ADDR[33..5] identify the 32-byte cache block which the <strong>CPU</strong> was attempting to read when the error occurred. In the 21064, if the FILL_IRD bit of the BIU_STAT register is clear, indicating that the error occurred during a D-stream cache fill, then FILL_ADDR[4..2] contain bits [4..2] of the physical address generated by the load instruction which triggered the cache fill. If FILL_IRD is set, then FILL_ADDR[4..2] are UNPREDICTABLE. FILL_ ADDR[63..34] and FILL_ADDR[1..0] read as zero. Functions Located on the DECchip 21064 77
Copyright © 1993 Digital Equipment Corporation. 3.9.10 Fill Syndrome Register (FILL_SYNDROME) The FILL_SYNDROME register is a 14-bit read-only register. If the chip is in EDC mode and an EDC error is recognized during a primary cache fill operation, the syndrome bits associated with the bad quadword are locked in the FILL_SYNDROME register. FILL_SYNDROME[6..0] contain the syndrome associated with the lower longword of the quadword, and FILL_SYNDROME[13..7] contain the syndrome associated with the upper longword of the quadword. A syndrome value of zero means that no errors where found in the associated longword. See Table 25 for a list of syndromes associated with correctable single-bit errors. The FILL_SYNDROME register is unlocked when the FILL_ADDR register is read. If the chip is in parity mode and a parity error is recognized during a primary cache fill operation, the FILL_SYNDROME register indicates which of the longword in the quadword got bad parity. FILL_SYNDROME[0] is set to indicate that the low longword was corrupted, and FILL_SYNDROME[7] is set to indicate that the high longword was corrupted. FILL_SYNDROME[13..8] and [6..1] are RAZ in parity mode. Figure 38: Fill Syndrome Table 25: Syndromes for Single-Bit Errors 6 3 1 1 4 3 0 0 7 6 RAZ HI[6..0] LO[6..0] 0 0 FILL_SYNDROME Data Bit Syndrome(Hex) Check Bit Syndrome(Hex) 00 4F 00 01 01 4A 01 02 02 52 02 04 03 54 03 08 04 57 04 10 05 58 05 20 06 5B 06 40 07 5D 08 23 09 25 10 26 11 29 78 Functions Located on the DECchip 21064
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 93: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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