Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

3.9.6 Data Cache Address Register (DC_ADDR) Copyright © 1993 Digital Equipment Corporation. In the 21064, this is a pseudo-register used for unlocking DC_STAT. In the 21064, DC_STAT and DC_ADDR are unlocked when DC_ADDR is read. Functions Located on the DECchip 21064 73
Copyright © 1993 Digital Equipment Corporation. 3.9.7 Bus Interface Unit Status Register (BIU_STAT) BIU_STAT is a read-only IPR. When one of BIU_HERR, BIU_SERR, BC_TPERR or BC_TCPERR is set, BIU_ STAT[6..0] are locked against further updates, and the address associated with the error is latched and locked in the BIU_ADDR register. BIU_STAT[6..0] and BIU_ ADDR are also spuriously locked when a parity error or an uncorrectable EDC error occurs during a primary cache fill operation. BIU_STAT[7..0] and BIU_ADDR are unlocked when the BIU_ADDR register is read. When FILL_EDC or BIU_DPERR is set, BIU_STAT[13..8] are locked against further updates, and the address associated with the error is latched and locked in the FILL_ ADDR register. BIU_STAT[14..8] and FILL_ADDR are unlocked when the FILL_ ADDR register is read. This register is not unlocked or cleared by reset and needs to be explicitly cleared by PALcode. Figure 37: BIU_STAT 63 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAZ RO RO RO RO R A Z RO RO RO RO RO RO RO 74 Functions Located on the DECchip 21064 BIU_HERR BIU_SERR BC_TPERR BC_TCPERR BIU_CMD FATAL1 FILL_EDC FILL_DPERR FILL_IRD FILL_QW FATAL2 BIU_STAT
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 39 and 40: Copyright © 1993 Digital Equipment
Page 89: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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