Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

8.4.3 Invalid Address - Bus Time-out ................................. 187 8.5 I/O Subsystem Errors ........................................... 188 8.6 C_ERR L Assertion . . ........................................... 188 Chapter 9 CPU POWERUP AND INITIALIZATION ................... 189 9.1 Processor Initialization .......................................... 189 9.1.1 Internal Processor Registers ................................... 189 9.1.2 Internal JSR stack ........................................... 189 9.2 B-Cache Initialization ........................................... 189 9.2.1 LDQ Data Format - BCC ENABLE B-CACHE INIT Set .............. 190 9.3 Duplicate Tag Store Initialization .................................. 191 9.4 System-bus Interface Initialization ................................. 191 9.5 CPU clocks and reset ........................................... 191 9.6 Power-up Sequence . . ........................................... 191 9.7 Powering Up with Bad Main Memory ............................... 192 Chapter 10 OVERVIEW OF THE CPU TESTABILITY FEATURES ...... 193 10.1 Bus Verification ............................................... 193 10.1.1 Address .................................................. 193 10.1.2 Data . . ................................................... 193 10.2 C4 EDC Generators ........................................... 193 10.3 C4 EDC Checkers . . ........................................... 194 10.4 DECchip 21064 EDC Checkers ................................... 194 10.5 DECchip 21064 EDC Generators ................................. 194 10.6 C4 Cobra-bus Probe Predicted Tag Parity Generator .................. 194 10.7 B-Cache Data Store Verification .................................. 194 10.8 B-Cache Tag/Control Store Verification . . . .......................... 194 10.9 Performance Counters ......................................... 195 10.10 Brain Dead Module Errors . . ................................... 195 Chapter 11 PHYSICAL AND ELECTRICAL CHARACTERISTICS ...... 197 viii 11.1 CPU Module Physical Specification ................................ 197 11.2 SABLE CPU CONNECTOR PINNING . . . .......................... 197 11.3 CPU Module Max DC Power Requirement .......................... 203
11.4 Environmental Specifications - Class B modified . . . .................. 203 11.4.1 Temperature . . . ........................................... 203 11.4.1.1 Storage ................................................ 203 11.4.1.2 Operating . . . ........................................... 203 11.4.2 Relative Humidity .......................................... 203 11.4.2.1 Storage ................................................ 204 11.4.2.2 Operating . . . ........................................... 204 11.4.3 Altitude .................................................. 204 11.4.3.1 Storage ................................................ 204 11.4.3.2 Operating Altitude ....................................... 204 11.4.4 Airflow ................................................... 204 11.4.5 Contamination . . ........................................... 204 11.4.6 Mean Time Between Failure (MTBF) Rate ....................... 204 11.4.7 Electrical Characteristics . . ................................... 204 11.4.7.1 AC References ........................................... 204 11.4.8 Clock Description ........................................... 204 11.4.9 AC and DC Characteristics ................................... 208 Appendix A ALPHA ARCHITECTURE OPTIONS SUPPORTED ....... 211 Appendix B SABLE CPU MODULE REGISTER REFERENCE GUIDE ............................................................... 213 Appendix C COBRA SPECIFIC ( PRIVILEGED ARCHITECTURE LIBRARY CODE ) PALCODE .................................... 223 C.1 Introduction .................................................. 223 C.2 PAL Environment . . ........................................... 223 C.3 Special PAL Instructions ........................................ 224 C.3.1 HW_MFPR and HW_MTPR ................................... 225 C.3.2 HW_LD and HW_ST ......................................... 227 C.3.3 HW_REI .................................................. 228 C.4 PAL Entry Points . . . ........................................... 228 C.5 General PALmode Restrictions ................................... 231 C.5.1 21064 PAL Restrictions ....................................... 231 C.5.2 21064 Specific PALmode Restrictions . .......................... 234 C.6 Powerup . . ................................................... 235 C.7 TB Miss Flows ................................................ 237 C.7.1 ITB Miss .................................................. 237 C.7.2 DTB Miss ................................................. 238 C.8 Error Flows .................................................. 239 ix
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7: 7.1.1 Exception Handling ..........
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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