Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.9.1 Required PALcode Instructions
The PALcode instructions listed in Table 20 are described in the Alpha Architecture
Handbook.
Table 20: Required PALcode Instructions
Mnemonic Type Operation
HALT Privileged Halt processor
IMB Unprivileged I-stream memory barrier
3.9.2 Architecturally Reserved PALcode Instructions
The hardware-specific instructions shown in Table 21 are executed in the PALcode
environment. They produce OPCDEC exceptions if executed while not in the PALcode
environment. These instructions are mapped using the architecturally reserved
opcodes (PAL19, PAL1B, PAL1D, PAL1E, PAL1F). They can only be used while executing
chip-specific PALcode.
Table 21: Instructions Specific to the 21064
Mnemonic Type Operation
HW_MTPR PALmode, Privileged Move data to processor register
HW_MFPR PALmode, Privileged Move data from processor register
HW_LD PALmode, Privileged Load data from memory
HW_ST PALmode, Privileged Store data in memory
HW_REI PALmode, Privileged Return from PALmode exception
Programming note: PALcode uses the HW_LD and HW_ST instructions to access
memory outside of the realm of normal Alpha AXP memory management.
3.9.3 PAL_TEMPs
The 21064 contains 32 registers that provide temporary storage for PALcode. These
registers are accessible through HW_MXPR instructions.
3.9.4 Data Cache Status Register (C_STAT)
The DC_STAT is a read-only IPR and is for diagnostic use only.
In order to use this register, software must first execute the following instruction
before executing the load or store, whose D-cache probe result is recorded in DC_
HIT.
HW_MTPR R31, 4B (hex)
70 Functions Located on the DECchip 21064