Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
• No floating point operate instruction can be issued exactly five or exactly six
cycles before a floating point divide completes.
3.8.5 Dual Issue Table
Table 19 can be used to determine instruction pairs that can issue in a single cycle.
Instructions are dispatched using two internal data paths or buses. For more
information about instructions and their opcodes and definitions, refer to the Alpha
Architecture Handbook.
The buses are referred to in Table 19 as IB0, IB1, and IBx.
Any instruction identified with IB0 in the table can be issued in the same cycle as
any instruction identified with IB1. An instruction that is identified as IBx may be
issued with either IB0 or IB1.
Dual issue is attempted if the input operands are available as defined by the
Producer-Consumer Latency Matrix (Figure 34) and the following requirements are
met:
• Two instructions must be contained within an aligned quadword.
• The instructions must not both be in the group labeled as IB0.
• The instructions must not both be in the group labeled as IB1.
• No more than one of JSR, integer conditonal branch, BSR, HW_REI, BR, or
floating-point branch can be issued in the same cycle.
• No more than one of load, store, HW_MTPR, HW_MFPR, MISC, TRAPB, HW_
REI, BSR, BR, OR JSR can be issued in the same cycle.
NOTE
Producer-Consumer latencies of zero indicate that dependent operations between
these two instruction classes can dual issue. For example, ADDQ R1,
R2, R3 STQ R3, D(R4).
68 Functions Located on the DECchip 21064