Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

3.7.3 Non-Issue Conditions Copyright © 1993 Digital Equipment Corporation. There are two basic reasons for non-issue conditions. • A pipeline freeze when a valid instruction or pair of instructions are prepared to issue but cannot due to a resource conflict This type of non-issue cycle can be minimized through code scheduling. • Pipeline bubbles when there is no valid instruction in the pipeline to issue Pipeline bubbles exist due to abort conditions as described in Section 3.7.2. In addition, a single pipeline bubble is produced whenever a branch-type instruction is predicted to be taken, including subroutine calls and returns. Pipeline bubbles are reduced directly by the hardware through bubble squashing, but can also be effectively minimized through careful coding practices. Bubble squashing involves the ability of the first four pipeline stages to advance whenever a bubble is detected in the pipeline stage immediately ahead of it while the pipeline is otherwise frozen. 3.8 Scheduling and Issuing Rules Scheduling and issuing rules are covered in the sections that follow. 3.8.1 Instruction Class Definition The scheduling and dual issue rules covered in this section are only performance related. There are no functional dependencies related to scheduling or dual issuing. The scheduling and issuing rules are defined in terms of instruction classes. Table 18 specifies all of the instruction classes and the box that executes the particular class. Functions Located on the DECchip 21064 63
Copyright © 1993 Digital Equipment Corporation. Table 18: Producer-Consumer Classes Class Name Box Instruction List LD Abox All loads, (HW_MFPR, RPCC, RS, RC, STC producers only), (FETCH consumer only) ST Abox All stores, HW_MTPR IBR Ebox Integer conditional branches FBR Fbox Floating point conditional branches JSR Ebox Jump to subroutine instructions JMP, JSR, RET, or JSR_COROUTINE, (BSR, BR producer only) IADDLOG Ebox ADDL ADDL/V ADDQ ADDQ/V SUBL SUBL/V SUBQ SUBQ/V S4ADDL S4ADDQ S8ADDL S8ADDQ S4SUBL S4SUBQ S8SUBL S8SUBQ LDA LDAH AND BIS XOR BIC ORNOT EQV SHIFTCM Ebox SLL SRL SRA EXTQL EXTLL EXTWL EXTBL EXTQH EXTLH EX- TWH MSKQL MSKLL MSKWL MSKBL MSKQH MSKLH MSKWH INSQL INSLL INSWL INSBL INSQH INSLH INSWH ZAP ZAP- NOT CMOVEQ CMOVNE CMOVLT CMOVLE CMOVGT CMOVGE CMOVLBS CMOVLBC ICMP Ebox CMPEQ CMPLT CMPLE CMPULT CMPULE CMPBGE IMULL Ebox MULL MULL/V IMULQ Ebox MULQ MULQ/V UMULH FPOP Fbox Floating point operates except divide FDIV Fbox Floating point divide 64 Functions Located on the DECchip 21064
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 29 and 30: Copyright © 1993 Digital Equipment
Page 79: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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