Sable CPU Module Specification
Sable CPU Module Specification Sable CPU Module Specification
8.4.3 Invalid Address - Bus Time-out ................................. 187 8.5 I/O Subsystem Errors ........................................... 188 8.6 C_ERR L Assertion . . ........................................... 188 Chapter 9 CPU POWERUP AND INITIALIZATION ................... 189 9.1 Processor Initialization .......................................... 189 9.1.1 Internal Processor Registers ................................... 189 9.1.2 Internal JSR stack ........................................... 189 9.2 B-Cache Initialization ........................................... 189 9.2.1 LDQ Data Format - BCC ENABLE B-CACHE INIT Set .............. 190 9.3 Duplicate Tag Store Initialization .................................. 191 9.4 System-bus Interface Initialization ................................. 191 9.5 CPU clocks and reset ........................................... 191 9.6 Power-up Sequence . . ........................................... 191 9.7 Powering Up with Bad Main Memory ............................... 192 Chapter 10 OVERVIEW OF THE CPU TESTABILITY FEATURES ...... 193 10.1 Bus Verification ............................................... 193 10.1.1 Address .................................................. 193 10.1.2 Data . . ................................................... 193 10.2 C4 EDC Generators ........................................... 193 10.3 C4 EDC Checkers . . ........................................... 194 10.4 DECchip 21064 EDC Checkers ................................... 194 10.5 DECchip 21064 EDC Generators ................................. 194 10.6 C4 Cobra-bus Probe Predicted Tag Parity Generator .................. 194 10.7 B-Cache Data Store Verification .................................. 194 10.8 B-Cache Tag/Control Store Verification . . . .......................... 194 10.9 Performance Counters ......................................... 195 10.10 Brain Dead Module Errors . . ................................... 195 Chapter 11 PHYSICAL AND ELECTRICAL CHARACTERISTICS ...... 197 viii 11.1 CPU Module Physical Specification ................................ 197 11.2 SABLE CPU CONNECTOR PINNING . . . .......................... 197 11.3 CPU Module Max DC Power Requirement .......................... 203
11.4 Environmental Specifications - Class B modified . . . .................. 203 11.4.1 Temperature . . . ........................................... 203 11.4.1.1 Storage ................................................ 203 11.4.1.2 Operating . . . ........................................... 203 11.4.2 Relative Humidity .......................................... 203 11.4.2.1 Storage ................................................ 204 11.4.2.2 Operating . . . ........................................... 204 11.4.3 Altitude .................................................. 204 11.4.3.1 Storage ................................................ 204 11.4.3.2 Operating Altitude ....................................... 204 11.4.4 Airflow ................................................... 204 11.4.5 Contamination . . ........................................... 204 11.4.6 Mean Time Between Failure (MTBF) Rate ....................... 204 11.4.7 Electrical Characteristics . . ................................... 204 11.4.7.1 AC References ........................................... 204 11.4.8 Clock Description ........................................... 204 11.4.9 AC and DC Characteristics ................................... 208 Appendix A ALPHA ARCHITECTURE OPTIONS SUPPORTED ....... 211 Appendix B SABLE CPU MODULE REGISTER REFERENCE GUIDE ............................................................... 213 Appendix C COBRA SPECIFIC ( PRIVILEGED ARCHITECTURE LIBRARY CODE ) PALCODE .................................... 223 C.1 Introduction .................................................. 223 C.2 PAL Environment . . ........................................... 223 C.3 Special PAL Instructions ........................................ 224 C.3.1 HW_MFPR and HW_MTPR ................................... 225 C.3.2 HW_LD and HW_ST ......................................... 227 C.3.3 HW_REI .................................................. 228 C.4 PAL Entry Points . . . ........................................... 228 C.5 General PALmode Restrictions ................................... 231 C.5.1 21064 PAL Restrictions ....................................... 231 C.5.2 21064 Specific PALmode Restrictions . .......................... 234 C.6 Powerup . . ................................................... 235 C.7 TB Miss Flows ................................................ 237 C.7.1 ITB Miss .................................................. 237 C.7.2 DTB Miss ................................................. 238 C.8 Error Flows .................................................. 239 ix
- Page 1 and 2: Sable CPU Module Specification This
- Page 3 and 4: CONTENTS Preface ..................
- Page 5 and 6: 3.9.6 Data Cache Address Register (
- Page 7: 7.1.1 Exception Handling ..........
- Page 11 and 12: 25 MM_CSR .........................
- Page 13 and 14: 27 Base Addresses for CSRs . . . ..
- Page 15 and 16: Preface Scope and Organization of t
- Page 17 and 18: Copyright © 1993 Digital Equipment
- Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
- Page 21 and 22: Copyright © 1993 Digital Equipment
- Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
- Page 25 and 26: Copyright © 1993 Digital Equipment
- Page 27 and 28: Copyright © 1993 Digital Equipment
- Page 29 and 30: Copyright © 1993 Digital Equipment
- Page 31 and 32: Copyright © 1993 Digital Equipment
- Page 33 and 34: Copyright © 1993 Digital Equipment
- Page 35 and 36: Copyright © 1993 Digital Equipment
- Page 37 and 38: Copyright © 1993 Digital Equipment
- Page 39 and 40: Copyright © 1993 Digital Equipment
- Page 41 and 42: Copyright © 1993 Digital Equipment
- Page 43 and 44: Copyright © 1993 Digital Equipment
- Page 45 and 46: Copyright © 1993 Digital Equipment
- Page 47 and 48: Copyright © 1993 Digital Equipment
- Page 49 and 50: Copyright © 1993 Digital Equipment
- Page 51 and 52: Copyright © 1993 Digital Equipment
- Page 53 and 54: Copyright © 1993 Digital Equipment
- Page 55 and 56: Copyright © 1993 Digital Equipment
- Page 57 and 58: Copyright © 1993 Digital Equipment
8.4.3 Invalid Address - Bus Time-out ................................. 187<br />
8.5 I/O Subsystem Errors ........................................... 188<br />
8.6 C_ERR L Assertion . . ........................................... 188<br />
Chapter 9 <strong>CPU</strong> POWERUP AND INITIALIZATION ................... 189<br />
9.1 Processor Initialization .......................................... 189<br />
9.1.1 Internal Processor Registers ................................... 189<br />
9.1.2 Internal JSR stack ........................................... 189<br />
9.2 B-Cache Initialization ........................................... 189<br />
9.2.1 LDQ Data Format - BCC ENABLE B-CACHE INIT Set .............. 190<br />
9.3 Duplicate Tag Store Initialization .................................. 191<br />
9.4 System-bus Interface Initialization ................................. 191<br />
9.5 <strong>CPU</strong> clocks and reset ........................................... 191<br />
9.6 Power-up Sequence . . ........................................... 191<br />
9.7 Powering Up with Bad Main Memory ............................... 192<br />
Chapter 10 OVERVIEW OF THE <strong>CPU</strong> TESTABILITY FEATURES ...... 193<br />
10.1 Bus Verification ............................................... 193<br />
10.1.1 Address .................................................. 193<br />
10.1.2 Data . . ................................................... 193<br />
10.2 C4 EDC Generators ........................................... 193<br />
10.3 C4 EDC Checkers . . ........................................... 194<br />
10.4 DECchip 21064 EDC Checkers ................................... 194<br />
10.5 DECchip 21064 EDC Generators ................................. 194<br />
10.6 C4 Cobra-bus Probe Predicted Tag Parity Generator .................. 194<br />
10.7 B-Cache Data Store Verification .................................. 194<br />
10.8 B-Cache Tag/Control Store Verification . . . .......................... 194<br />
10.9 Performance Counters ......................................... 195<br />
10.10 Brain Dead <strong>Module</strong> Errors . . ................................... 195<br />
Chapter 11 PHYSICAL AND ELECTRICAL CHARACTERISTICS ...... 197<br />
viii<br />
11.1 <strong>CPU</strong> <strong>Module</strong> Physical <strong>Specification</strong> ................................ 197<br />
11.2 SABLE <strong>CPU</strong> CONNECTOR PINNING . . . .......................... 197<br />
11.3 <strong>CPU</strong> <strong>Module</strong> Max DC Power Requirement .......................... 203
Change language