Sable CPU Module Specification

3.6 Cache Organization
Copyright © 1993 Digital Equipment Corporation.
The 21064 includes two on-chip caches, a data cache (Dcache) and an instruction
cache (Icache). All memory cells in both Dcache and Icache are fully static six transistor
CMOS structures.
3.6.1 Data Cache (Dcache)
The DECchip DECchip 21064 Dcache contains an 8 KB (16 KB for the DECchip
21064-A275 ) data cache. It is a write-through, direct mapped, read allocate physical
cache and has 32-byte blocks. System components can keep the Dcache coherent
with memory by using the invalidate bus described in the pin bus section of this
specification.
3.6.2 Instruction Cache (Icache)
The DECchip 21064 Icache is an 8-KB (16-KB for the DECchip 21064-A275), physical
direct-mapped cache. Icache blocks, or lines, contain 32-bytes of instruction stream
data with associated tag, as well as a six-bit ASN field, a one-bit ASM field, and an
eight-bit branch history field per block. It does not contain hardware for maintaining
coherency with memory and is unaffected by the invalidate bus.
The chip also contains a single-entry Icache stream buffer that, together with its
supporting logic, reduces the performance penalty due to Icache misses incurred
during in-line instruction processing. Stream buffer prefetch requests never cross
physical page boundaries, but instead wrap around to the first block of the current
page.
3.7 Pipeline Organization
The 21064 has a seven-stage pipeline for integer operate and memory reference instructions.
Floating point operate instructions progress through a ten stage pipeline.
The Ibox maintains state for all pipeline stages to track outstanding register writes,
and determine Icache hit/miss.
The following figures show the integer operate, memory reference, and the floating
point operate pipelines for the Ibox, Ebox, Abox, and Fbox. The first four cycles are
executed in the Ibox and the last stages are box specific. There are bypassers in
all of the boxes that allow the results of one instruction to be used as operands of
a following instruction without having to be written to the register file. Section 3.8
describes the pipeline scheduling rules.
Functions Located on the DECchip 21064 59