Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Because the result of each Dcache lookup is known late in the pipeline (stage [6]) and
instructions are issued in pipe stage [3], there can be two instructions in the Abox
pipeline behind a load instruction that misses the Dcache. These two instructions
are handled as follows:
• Loads that hit the Dcache are allowed to complete - hit under miss.
• Load misses are placed in a silo and replayed in order after the first load miss
completes.
• Store instructions are presented to the Dcache at their normal time with respect
to the pipeline. They are siloed and presented to the write buffer in order with
respect to load misses.
In order to improve performance, the Ibox is allowed to restart the execution of
Abox directed instructions before the last pending Dcache fill is complete. Dcache fill
transactions result in four data transfers from the BIU to the Dcache. These transfers
can each be separated by one or more cycles depending on the characteristics of the
external cache and memory subsystems. The BIU attempts to send the quadword of
the fill block that the CPU originally requested in the first of these four transfers (it
is always able to accomplish this for reads that hit in the external cache). Therefore,
the pending load instruction that requested the Dcache fill can complete before the
Dcache fill finishes. Dcache fill data accumulates one quadword at a time into a
"pending fill" latch, rather than being written into the cache array as it is received
from the BIU. When the load miss silo is empty and the requested quadword for the
last outstanding load miss is received, the Ibox resumes execution of Abox-directed
instructions despite the still-pending Dcache fill. When the entire cache line has
been received from the BIU, it is written into the Dcache data array whenever the
array is not busy with a load or a store.
3.3.20 Write Buffer
The Abox contains a write buffer for two purposes.
• To minimize the number of CPU stall cycles by providing a high bandwidth (but
finite) resource for receiving store data
This is required since the 21064 can generate store data at the peak rate of one
quadword every CPU cycle, which is greater than the rate at which the external
cache subsystem can accept the data.
• To attempt to aggregate-store data into aligned 32-byte cache blocks to maximize
the rate at which data may be written from the 21064 into the external cache
The write-merging operation of the write buffer may result in the order of off-chip
writes being different from the order in which their corresponding store instructions
were executed. Further, the write buffer may collapse multiple stores to the same
location into a single off-chip write transaction. Software that requires strict write
ordering, or that multiple stores to the same location result in multiple off-chip write
sequences, must insert a memory barrier instruction between the store instructions
of interest.
Functions Located on the DECchip 21064 55