Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
The 21064 DTB supports a single address space number (ASN) with the PTE[ASM]
bit. Each PTE entry in the DTB contains an address space match (ASM) bit. Writes
to the DTBASM IPR invalidate all entries that do not have their ASM bit set. This
provides a simple method of preserving entries that map operating system regions
while invalidating all others.
For load and store instructions, the effective 43-bit virtual address is presented to
the DTBs. If the PTE of the supplied virtual address is cached in the DTB, the PFN
and protection bits for the page that contains the address are used by the Abox to
complete the address translation and access checks.
The DTB is filled and maintained by PALcode. Note that the DTB can be filled in
kernel mode by setting the HWE bit in the ICCSR IPR.
3.3.18 Bus Interface Unit (BIU)
The BIU controls the interface to the 21064 pin bus. The BIU responds to three
classes of CPU-generated requests:
• Dcache fills
• Icache fills
• Write buffer-sourced commands
The BIU resolves simultaneous internal requests using a fixed priority scheme in
which Dcache fill requests are given highest priority, followed by Icache fill requests.
Write buffer requests have the lowest priority.
The BIU contains logic to directly access an external cache to service internal cache
fill requests and writes from the write buffer. The BIU services reads and writes
that do not hit in the external cache with help from external logic.
Internal data transfers between the CPU and the BIU are made through a 64-bit
bidirectional bus. Since the internal cache fill block size is 32 bytes, cache fill operations
result in four data transfers across this bus from the BIU to the appropriate
cache. Also, because each write buffer entry is 32 bytes wide, write transactions may
result in four data transfers from the write buffer to the BIU.
3.3.19 Load Silos
The Abox contains a memory reference pipeline that can accept a new load or store
instruction every cycle until a Dcache fill is required. Since the Dcache lines are only
allocated on load misses, the Abox can accept a new instruction every cycle until a
load miss occurs. When a load miss occurs the Ibox stops issuing all instructions
that use the load port of the register file or are otherwise handled by the Abox. This
includes LDx, STx, HW_MTPR, HW_MFPR, FETCH, FETCH_M, RPCC, RS, RC,
and MB. It also includes all memory format branch instructions, JMP, JSR, JSR_
COROUTINE, and RET.
However, a JSR with a destination of R31 may be issued.
54 Functions Located on the DECchip 21064