Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 13 (Cont.): BIU Control Register Description
Field Description
Backup cache physical address disable - This 4-bit field may be used to prevent the CPU chip
from using the external cache to service reads and writes based on the quadrant of physical
address space which they reference. Table 16 shows the correspondence between this bit field
and the physical address space.
When a read or write reference is presented to the bus interface unit (BIU), the values of BC_
PA_DIS, BC_ENA, and physical address bits together determine whether or not to try
using the external cache to satisfy the reference. If the external cache is not to be used for a
given reference, the bus interface unit does not probe the tag store and makes the appropriate
system request immediately. The value of BC_PA_DIS has no impact on which portions of the
physical address space may be cached in the primary caches. System components control this
through the RDACK field of the pin bus. BC_PA_DIS is not initialized by a reset.
31 BAD_TCP [ write-only ]
BAD Tag Control Parity - When set, BAD_TCP causes the 21064 CPU to write bad parity into
the tag control RAM whenever it does a fast external RAM write.
30:28 BC_SIZE [ write-only ]
Backup Cache Size - This field is used to indicate the size of the external cache. BC_SIZE is
not initialized by a reset and must be explicitly written before enabling the backup cache. (See
Table 15 for the encodings.)
27:13 BC_WE_CTL[15:1] [ write-only ]
Backup Cache Write Enable Control. This field controls the timing of the write enable and chip
enable pins during writes into the data and tag control RAMs. It consists of 15 bits, where each
bit determines the value placed on the write enable and chip enable pins during a given CPU
cycle of the RAM write access.
When a given bit of BC_WE_CTL is set, the write enable and chip enable pins are asserted
during the corresponding CPU cycle of the RAM access. BC_WE_CTL (bit 13 in BIU_CTL)
corresponds to the second cycle of the write access, BC_WE_CTL (bit 14 in BIU_CTL) to
the third CPU cycle, and so on. The write enable pins are never asserted in the first CPU cycle
of a RAM write access.
Unused bits in the BC_WE_CTL field must be written with 0s.
BC_WE_CTL is not initialized on reset and must be explicitly written before enabling the external
backup cache.
12 DELAY_WDATA [ write-only ]
DELAY_DATA
11:8 BC_WR_SPD [ write-only ]
Backup cache write speed. This field indicates to the bus interface unit the write cycle time of
the RAMs used to implement the off-chip external cache, (Backup cache on the CPU module),
measured in CPU cycles. It should be written with a value equal to one less the write cycle time
of the external cache RAMs.
Access times for writes must be in the range 16..2 CPU cycles, which means the values for the
BC_WR_SPD field are in the range of 15..1.
BC_WR_SPD is not initialized on reset and must be explicitly written before enabling the external
cache.
7:4 BC_RD_SPD [ write-only ]
48 Functions Located on the DECchip 21064