Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.3.13 Alternative Processor Mode Register (ALT_MODE)
ALT_MODE is a write-only IPR. The AM field specifies the alternate processor mode
used by HW_LD and HW_ST instructions which have their ALT bit (bit 14) set.
Figure 28: ALT_MODE
6
3
Table 12: ALT Mode
ALT_MODE[4..3] Mode
0 0 Kernel
0 1 Executive
1 0 Supervisor
1 1 User
3.3.14 Cycle Counter Register (CC)
0
5
00
43
0
2
IGN
A
M IGN
The 21064 supports a cycle counter as described in the Alpha Architecture Handbook.
This counter, when enabled, increments once each CPU cycle. HW_MTPR Rn,CC
writes CC[63..32] with the value held in Rn[63..32], and CC[31..0] are not changed.
This register is read by the RPCC instruction defined by the Alpha AXP Architecture.
3.3.15 Cycle Counter Control Register (CC_CTL)
HW_MTPR Rn,CC_CTL writes CC[31..0] with the value held in Rn[31..0], and
CC[63..32] are not changed. CC[3..0] must be written with zero. If Rn[32] is set
then the counter is enabled, otherwise the counter is disabled. CC_CTL is a writeonly
IPR.
3.3.16 Bus Interface Unit Control Register (BIU_CTL)
The following figures and tables show the bus interface unit control register format
and field descriptions.
46 Functions Located on the DECchip 21064
0
0