Sable CPU Module Specification

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Figure 26: DECchip 21064 ABOX_CTL 6 3 DC_FHIT DC_ENA NCACHE_NDISTURB STC_NORESULT EMD_EN SPE_2 SPE_1 IC_SBUF_EN CRD_EN MCHK_EN WB_DIS MBZ 1 1 2 1 Copyright © 1993 Digital Equipment Corporation. 1 0 0 9 0 8 0 7 0 6 0 5 Functions Located on the DECchip 21064 43 0 4 0 3 0 2 0 1 0 0

Copyright © 1993 Digital Equipment Corporation. Figure 27: DECchip 21064-A275 ABOX_CTL 63 15 14 13 12 11 10 9 MBZ 44 Functions Located on the DECchip 21064 8 7 6 5 4 3 2 1 0 WB_DIS MCHK_EN CRD_EN IC_SBUF_EN SPE_1 SPE_2 EMD_EN STC_NORESULT NCACHE_NDISTURB DC_ENA DC_FHIT DC_16K F_TAG_ERR NOCHK_PAR DOUBLE_INVAL

Page 1 and 2: Sable CPU Module Specification This

Page 3 and 4: CONTENTS Preface ..................

Page 5 and 6: 3.9.6 Data Cache Address Register (

Page 7 and 8: 7.1.1 Exception Handling ..........

Page 9 and 10: 11.4 Environmental Specifications -

Page 11 and 12: 25 MM_CSR .........................

Page 13 and 14: 27 Base Addresses for CSRs . . . ..

Page 15 and 16: Preface Scope and Organization of t

Page 17 and 18: Copyright © 1993 Digital Equipment

Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND


Page 23 and 24: 1.2 The Alpha AXP Architecture Copy


















Page 59: Copyright © 1993 Digital Equipment



















Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE


Page 103 and 104: Figure 41: B-Cache Control Register

Page 105 and 106: Table 28 (Cont.): B-Cache Control R

Page 107 and 108: Table 28 (Cont.): B-Cache Control R







Page 121 and 122: 4.3.1 Duplicate Tag Error Register

Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co

Page 125 and 126: Table 37: System-bus Control Regist

Page 127 and 128: 4.7.2 System-bus Error Register - C

Page 129 and 130: Table 38: System-bus Error Register

Page 131 and 132: Table 38 (Cont.): System-bus Error

Page 133 and 134: 4.7.3 System-bus Error Address Low


Page 137 and 138: 4.8 Multiprocessor Configuration CS

Page 139 and 140: 4.9 System Interrupt Clear Register

Page 141 and 142: 4.10 Address Lock Register - CSR13

Page 143 and 144: 4.11 Miss Address Register - CSR14

Page 145 and 146: Table 46 (Cont.): C4 Revision Regis

Page 147 and 148: Table 48 (Cont.): Interval Timer In

Page 149 and 150: Table 50: D-bus Microcontroller Clo

Page 151 and 152: Figure 58: Granting Order rule 4 CP


Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des

Page 157 and 158: Table 57: CPU EEPROM Defaults Locat



























Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL

Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1

Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S

Page 217 and 218: 11.3 CPU Module Max DC Power Requir


Page 221 and 222: Figure 68: module clocks Cobra - b

Page 223 and 224: Table 85 (Cont.): System bus AC and

Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
















Page 257 and 258: INDEX 21064 IEEE floating point con

Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating

Page 261: STQC cycle, 144 STxC cycle, 144 STx

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