Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

4.11 Miss Address Register - CSR14 ................................... 127 4.11.1 C4 Revision Register - CSR15 ................................. 128 4.12 Interval Timer ............................................... 130 4.13 D-bus . . . ................................................... 131 4.14 System-bus Arbiter . ........................................... 133 4.15 System-bus CRESET L Generation ................................ 136 4.15.1 Sable CPU Non-Volatile EEPROM .............................. 137 Chapter 5 CPU MODULE TRANSACTIONS ......................... 143 5.1 Processor Transactions .......................................... 143 5.1.1 21064 Processor TRANSACTIONS .............................. 146 5.1.1.1 FAST EXTERNAL CACHE READ HIT ........................ 146 5.1.1.2 FAST EXTERNAL CACHE WRITE HIT ....................... 147 5.1.1.3 READ_BLOCK TRANSACTION .............................. 148 5.1.1.4 WRITE_BLOCK .......................................... 150 5.1.1.5 LDxL TRANSACTION . . ................................... 152 5.1.1.6 StxC TRANSACTION . . . ................................... 152 5.1.1.7 BARRIER TRANSACTION .................................. 153 5.1.1.8 FETCH TRANSACTION ................................... 153 5.1.1.9 FETCHM TRANSACTION .................................. 154 5.1.2 Cacheable vs Non-Cacheable vs Allocate-Invalid . .................. 155 5.2 System-bus Transactions ........................................ 156 5.2.1 CPU as Commander ......................................... 157 5.2.2 CPU as Bystander ........................................... 157 5.2.3 CPU as Responder ........................................... 157 5.3 Control Flow of CPU Module Transactions . .......................... 158 5.3.1 Processor Initiated ........................................... 158 5.3.2 System-bus Initiated ......................................... 162 Chapter 6 CACHE INVALIDATE MANAGEMENT .................... 165 6.1 Processor Caused Invalidates . . ................................... 165 6.2 C-bus Caused Invalidates ........................................ 165 Chapter 7 EXCEPTIONS AND INTERRUPTS ........................ 167 vi 7.1 Processor Generated . ........................................... 167
7.1.1 Exception Handling .......................................... 168 7.1.1.1 PAL Priority Level ........................................ 169 7.1.1.2 PALcode 0020 Entry Characteristics .......................... 169 7.1.1.3 PAL Routine Behavior . . ................................... 169 7.1.1.3.1 B-Cache Tag Parity Error ................................ 169 7.1.1.3.2 B-Cache Tag Control Parity Error .......................... 170 7.1.1.3.3 B-Cache Data Single Bit EDC Error ........................ 170 7.1.1.3.4 B-Cache Data Uncorrectable EDC Error . . . .................. 170 7.1.1.3.5 B-Cache Data Single Bit EDC Error ........................ 171 7.1.1.3.6 B-Cache Data Uncorrectable EDC Error . . . .................. 171 7.1.1.3.7 21064 Data bus Single Bit EDC Error ....................... 171 7.1.1.3.8 21064 Data bus Uncorrectable EDC Error . .................. 171 7.1.1.3.9 B-Cache Tag or Tag Control Parity Error . . .................. 172 7.1.1.3.10 Cobra-bus Parity Error ................................. 172 7.1.1.3.11 Invalid Cobra-bus Address ............................... 172 7.1.1.3.12 Other CPU Errors . . ................................... 173 7.1.1.3.13 Main Memory Uncorrectable EDC Errors . .................. 173 7.2 Non-processor Generated ........................................ 173 7.2.1 Interrupt Handling .......................................... 173 7.2.1.1 PAL Priority Level ........................................ 174 7.2.1.2 PALcode 00E0 Entry Characteristics .......................... 174 7.2.1.3 Hardware 0 - Hardware Error ............................... 175 7.2.1.4 Hardware 1 - Local I/O . . ................................... 177 7.2.1.5 Hardware 3 - Interprocessor ................................. 177 7.2.1.6 Hardware 4 - Interval Timer ................................ 177 7.2.1.7 Hardware 5 - System Events ................................ 177 7.2.1.8 Software X . . . ........................................... 178 7.2.1.9 Serial Line . . . ........................................... 178 7.2.1.10 Performance Counter X ................................... 178 7.2.1.11 Asynchronous System Trap ................................. 178 Chapter 8 FAULT MANAGEMENT/ERROR RECOVERY .............. 179 8.1 Processor Errors ............................................... 179 8.2 B-Cache Errors ................................................ 179 8.2.1 Tag and Tag Control Store Parity Errors .......................... 179 8.2.2 Data Store EDC Errors ....................................... 181 8.2.2.1 Correctable . . . ........................................... 181 8.2.2.2 Uncorrectable . ........................................... 183 8.3 Duplicate P-Cache Tag Store Parity Errors .......................... 186 8.4 System-bus Errors . . ........................................... 186 8.4.1 C/A Parity Error . ........................................... 186 8.4.2 Data Parity Error ........................................... 187 vii
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5: 3.9.6 Data Cache Address Register (
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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