Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.3.8 Data Translation Buffer ASM Register (DTBASM)
A write of any value to this IPR invalidates all 32 small-page and 4 large-page DTB
entries in which the ASM bit is equal to zero. The DTBASM is a pseudo-register.
3.3.9 Data Translation Buffer Invalidate Signal Register (DTBIS)
Any write to this pseudo-register will invalidate the DTB entry which maps the
virtual address held in the integer register. The integer register is identified by the
Rb field of the HW_MTPR instruction, used to perform the write.
3.3.10 Flush Instruction Cache Register (FLUSH_IC)
A write of any value to this pseudo-register flushes the entire instruction cache.
3.3.11 Flush Instruction Cache ASM Register (FLUSH_IC_ASM)
Any write to this pseudo-IPR invalidates all I-Cache blocks in which the ASM bit is
clear.
3.3.12 A-box Control Register (ABOX_CTL)
The Abox control register differs between the DECchip 21064 Figure 26 and the
DECchip 21064-A275 (Figure 27. The Abox for DECchip 21064-A275 uses bits
through , where the Abox for the DECchip 21064 keeps these as undefined.
42 Functions Located on the DECchip 21064